Analog Devices,inc.

Other

Christopher W Mangelsdorf

David H Robertson

Peter Real

Katsufumi Nakamura

Douglas A Mercer

Theodore L Tewksbury

Adrian P Brokaw

A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both sample and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus. Further, the apparatus includes a clamping circuit which servos a voltage at the output of the correlated double-sampling circuit to a desired voltage level at the input to the correlated double-sampling circuit and within the supply range and operating range of the apparatus.

Correlated double sampling method and apparatus

A variable gain amplifier includes an input transconductor having a transconductance that is variable in response to a first control signal, an output circuit having a transresistance that is variable in response to a second control signal and a gain controller responsive to a gain control signal x for providing the first and second control signals to the input transconductor and the output circuit. The amplifier has a voltage gain equal to the product of the transconductance and the transresistance. When the first control signal is a function (1+x) of the gain control signal and the second control signal is a function (1-x) of the gain control signal, the voltage gain of the amplifier is approximately an exponential function of the gain control signal.

Variable gain CMOS amplifier

Method and apparatus for providing an offset level to an image signal

A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both samples and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus. Further, the apparatus includes a clamping circuit which clamps a voltage at the output of the correlated double-sampling circuit to a desired voltage level at the input to the correlated double-sampling circuit and within the supply range and operating range of the apparatus.

Input clamping method and apparatus with a correlated double-sampling

A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.

Current mode sample-and-hold amplifier

An error correction testing system and method for a multistage A/D converter includes a testing device for disabling the correction circuit and indicating the code transitions of the first A/D converter relative to the code transitions of the second A/D converter representing error in the first A/D converter.

Error correction testing system and method for a multistage A/D converter

An analog-to-digital converter (ADC) having three cascaded A/D stages of the 'flash' type. In the first stage, the analog signal is compared with a set of threshold reference voltages so as to develop a set of most-significant bits and to produce two analog residue signals: (1) a normal residue corresponding to the difference between the analog input and the reference voltage next below the analog input, and (2) a second residue corresponding to the difference between the analog input and the reference voltage next above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage. The second A/D stage develops a set of less-significant bits and two more residue signals for the third A/D stage. The second stage further includes a capacitor network arranged to effectively double the operating range of that stage to accommodate error correction.

Correction range technique for multi-range A/D converter

An analog-to-digital converter (ADC) having two cascaded A/D stages of the parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage. The second A/D stage includes a parallel converter for developing a set of less-significant bits representing the ratio of the normal residue signal to the sum of the two residue signals. The most-significant and less-significant sets of bits are combined to provide the final digital output. Errors due to inaccuracies in interstage gain are reduced due to the use of two residue signals for generating the less-significant bits.

Multi-stage A/D converter

A pipelined multi-stage ADC in which residue signals are passed between stages as currents. All sample-and-hold circuits are designed to be current-in/current-out structures; all but one also provide a voltage output. A voltage representation of the analog signal is provided as input to the flash converter within the quantization loop of each stage, allowing implementation of a conventional voltage comparator architecture in the flash converter. An extra comparator is added to the flash converter and an extra segment is included in the DAC of each stage. Inputs above full scale and below zero can be converted and generate output codes. Whenever the input goes above full scale or below zero, an out-of-range bit is set and the digital outputs are set to all ones or all zeroes, respectively. The combination of out-of-range bit and digital codes tell whether overranging or underranging occurred.

Analog-to-digital converter employing a pipeline multi-stage architecture

A reference voltage distribution system for use on an integrated circuit to distribute, from a reference voltage input, to remote locations on the chip, precise images of the reference voltage. The system comprises (1) a reference buffer located proximate a reference input connection and (2) a plurality of remote generator blocks, one located at each of the remotely-located sub-blocks or circuits requiring an image of the reference voltage. The reference buffer generates from the reference voltage a number of precision currents, each proportional to the reference voltage. These precision currents are routed to the remote generator blocks. Each remote generator block converts its precision current into a precision reference voltage for local use. These latter reference voltages may be the same as or different from the reference voltage supplied to chip itself.

Reference voltage distribution system

The apparatus comprises a parallel analog-to-digital converter comprising a matrix of differentially coupled transistor pairs wherein the base of one transistor of each differential pair is coupled to a reference voltage and the base of the other transistor of each differential pair is coupled to the input voltage through a specified offset. In each row of differential pairs, the collectors of the transistors are alternately coupled to first and second row output points. The first and second row output points of each row are coupled to the inverting and non-inverting inputs, respectively of a comparator. Additional comparators are provided for comparing the second row output of each row with the first row output of the succeeding row. The matrix is arranged such that the combination of the comparator outputs is unique for each possible digital level in the full scale range of the converter. Logic circuitry is coupled to the comparator outputs to produce a computer usable code therefrom.

Parallel analog-to-digital converter

In a parallel (or 'flash') type analog-to-digital converter (ADC), a decoding technique and apparatus. First, the output of every comparator is examined relative to its nearest neighbors. If, for comparator 'n', the outputs of 'neighboring' comparators 'n+1' and 'n-1' both are in a different state than the output of comparator 'n', the output state of comparator 'n' is reversed. That is, each group of three adjacent comparators (n-1, n and n+1) is examined and the output of the 'center' comparator is 'corrected' by substituting the majority state of the three comparators for the output of the 'center' comparator (i.e., comparator 'n'). Second, the zeroes-to-ones transition point is found in the thus-corrected outputs. Once the transition point is found, a conventional encoding produces a digital output word. Circuitry is provided for the efficient implementation of the method and for performing the method in an equivalent single step.

Decoding circuit for flash-type analog-to-digital converter

An analog-to-digital converter in the form of an integrated circuit providing a plurality of parallel-connected sub-converters, each producing one bit of the output word. For any sub-converter, an elongate P-type diffusion (20) serves as the base of a multiple-emitter NPN transistor. The same diffusion (20) serves as the collector of a pair of lateral PNP transistors. The lateral transistors inject current into the central diffusion, resulting in a parabolic voltage distribution along its length. A differential analog input voltage applied to the ends of the central diffusion shifts the parabolic voltage peak longitudinally along the diffusion. The multiple emitters of the NPN transistor are connected alternately to output nodes and sense the position of the parabolic voltage peak to produce the binary output.

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Reading, MA, United States of America

Christopher W Mangelsdorf