Amberwave Systems Corporation

Massachusetts Institute of Technology

Taiwan Semiconductor Manufacturing Comp. Ltd.

Mtpv Power Corporation

Rochester Institute of Technology

Solexant Corporation

Mtpv, LLC

Christopher W Leitz

Matthew T Currie

Richard Charles Westhoff

Christopher J Vineis

Vicky K Yang

Eugene A Fitzgerald

Paul Greiff

Minjoo Larry Lee

Eric L Brown

Robert S DiMatteo

Anthony J Lochtefeld

Kevin Ryu

Renee D Lambert

Mayank T Bulsara

Donna-Ruth Webb Yost

Ryne P Raffaelle

Steven W Rabe

Brian F Aull

Vladimir Bolkhovsky

James A Gregory

Leslie G Fritzemeier

David Volfson

Daniel R Schuette

Joseph S Ciampi

Karl Alexander McIntosh

Robert Dimatteo

A chip-to-chip integration process for rapid prototyping of silicon avalanche photodiode (APD) arrays has been developed. This process has several advantages over wafer-level 3D integration, including: (1) reduced cost per development cycle since a dedicated full-wafer read-out integrated circuit (ROIC) fabrication is not needed, (2) compatibility with ROICs made in previous fabrication runs, and (3) accelerated schedule. The process provides several advantages over previous processes for chip-to-chip integration, including: (1) shorter processing time as the chips can be diced, bump-bonded, and then thinned at the chip-level faster than in a wafer-level back-illumination process, and (2) the CMOS substrate provides mechanical support for the APD device, allowing integration of fast microlenses directly on the APD back surface. This approach yields APDs with low dark count rates (DCRs) and higher radiation tolerance for harsh environments and can be extended to large arrays of APDs.

Rapid prototyping of single-photon-sensitive silicon avalanche photodiodes

A new process that enables void-free direct-bonded MBE-passivated large-format image sensors is disclosed. This process can be used to produce thin large-area image sensors for UV and soft x-ray imaging. Such devices may be valuable in future astronomy missions or in the radiology field. Importantly, by controlling the hydrogen concentration in the silicon oxide layers of the image sensor and the support wafer, voids in the bonding interface can be significantly reduced or eliminated. This process can be applied to any wafer that includes active circuitry and requires a second wafer, such as a support wafer.

Semiconductor surface passivation

Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Semiconductor heterostructures having reduced dislocation pile-ups and related methods

An MTPV thermophotovoltaic chip comprising a photovoltaic cell substrate, micron/sub-micron gap-spaced from a juxtaposed heat or infrared radiation-emitting substrate, with a radiation-transparent intermediate window substrate preferably compliantly adhered to the photovoltaic cell substrate and bounding the gap space therewith.

Submicron gap thermophotovoltaic structure and fabrication method

An improved submicron gap thermophotovoltaic structure and method comprising an emitter substrate with a first surface for receiving heat energy and a second surface for emitting infrared radiation across an evacuated submicron gap to a juxtaposed first surface of an infrared radiation-transparent window substrate having a high refractive index. A second surface of the infrared radiation-transparent substrate opposite the first surface is affixed to a photovoltaic cell substrate by an infrared-transparent compliant adhesive layer. Relying on the high refractive index of the infrared radiation-transparent window substrate, the low refractive index of the submicron gap and Snell's law, the infrared radiation received by the first surface of the infrared radiation-transparent window substrate is focused onto a more perpendicular path to the surface of the photovoltaic cell substrate. This results in increased electrical power output and improved efficiency by the thermophotovoltaic structure.

Submicron gap thermophotovoltaic structure and method

Sub-micrometer gap thermophotovoltaic structure (MTPV) and fabrication method therefor

A near-field energy conversion method, utilizing a sub-micrometer 'near-field' gap between juxtaposed infrared radiation receiver and emitter surfaces, wherein compliant membrane structures, preferably fluid-filled, are interposed in the structure for maintaining uniform gap separation. Thermally resistant gap spacers are also used to maintain uniform gap separation. Means are provided for cooling a receiver substrate structure and for conducting heat to an emitter substrate structure. The gap may also be evacuated for more effective operation.

Method and structure for providing a uniform micron/sub-micron gap separation within micro-gap thermophotovoltaic devices for the generation of electrical power

The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

Structure and method for a high-speed semiconductor device having a Ge channel layer

A semiconductor structure may include a polycrystalline substrate comprising a metal, the polycrystalline substrate having substantially randomly oriented grains, as well as a buffer layer disposed thereover. The buffer layer may comprise a plurality of islands having an average island spacing therebetween. A polycrystalline semiconductor layer is disposed over the buffer layer.

Polycrystalline semiconductor layers and methods for forming the same

A near-field energy conversion structure and method of assembling the same, utilizing a sub-micrometer 'near field' gap between juxtaposed photocell infrared radiation receiver and heat emitter surfaces, wherein compliant membrane structures, preferably fluid-filled, are interposed in the structure.

Method and structure, using flexible membrane surfaces, for setting and/or maintaining a uniform micron/sub-micron gap separation between juxtaposed photosensitive and heat-supplying surfaces of photovoltaic chips and the like for the generation of electrical power

A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

Methods of fabricating semiconductor devices having strained dual channel layers

Growing community of inventors

Nashua, NH, United States of America

Christopher W Leitz