Cypress Semiconductor Corporation

Christopher W Jones

Jeffery Mark Marshall

Jeffery Scott Hunt

George M Ansel

Steven J E Wilton

Hatem Yazbek

Andrew J Wright

David L Johnson

Richard L Kapusta

Rochan Sankar

Brenor L Brophy

Roger J Bettman

Anita X Meng

James B MacArthur

Kevin B Skahill

Michel J Campmas

Babar Raza

Christopher L Webb

Vinod Malhotra

Peter L Higginson

A programmable serial interface device. The device generally comprises a programmable logic device and another die mounted to an assembly apparatus. The programmable logic device may comprise (i) a plurality of logic block clusters and (ii) a plurality of routing channels configured to interconnect said logic block clusters. The die may comprise a first communication channel (i) configured to convert between a first serial data signal and a first parallel data signal and (ii) coupled to a first of the routing channels to exchange the first parallel data signal with at least one of the logic block clusters.

Programmable serial interface

A multi-chip integrated circuit assembly including embodiments having a plurality of integrated circuits connected thereto. According to one embodiment, a multi-chip assembly ( ) may include a first surface ( ) having first surface connections ( ) and a second surface ( ) having second surface connections ( ). A first surface ( ) may be lower than a second surface ( ). First and/or second surface connections ( and ) may have conductive paths to one another and/or to assembly connections ( ). In one particular arrangement, first and second surface connections ( and ) may provide &ldquo;flip-chip&rdquo; type connections to integrated circuits. Assembly connections ( ) may provide a ball grid array (BGA) type connection for the multi-chip assembly ( ).

Multi-die assembly

A configurable crossbar switching circuit within a programmable logic device capable of efficient, large scale switching and for cascading for implementing much larger switching functions. In one embodiment of the invention, the crossbar switch is integral to a programmable logic device. In one embodiment, the crossbar switching circuit is bus based, switching all of the conductors constituting a data bus substantially simultaneously and in their entirety as a bus unit. In one embodiment, the crossbar switching circuit performs switching operations unidirectionally. For the implementation of larger scale switching functions, one embodiment of the present invention exploits the cascadable character of the crossbar switching circuit. Cascading crossbar switches enables switching between differing numbers of inputs and outputs, even exceeding capacities of individual crossbars. In one embodiment, a permutation subcircuit allows the configuration of signals within the crossbar switch to a designated, programmed sequence and specific order.

Cascadable bus based crossbar switching in a programmable logic device

A programmable logic device comprising one or more macrocells and a product term array. The macrocells may comprise logic that may be configured to (i) generate and propagate a carry signal and (ii) generate a sum bit. The product term array may comprise two product terms per macrocell.

Reduced product term carry chain

A programmable logic device comprising one or more memory circuits configured to check a cyclic redundancy check (CRC) value of an input and generate a CRC for an output.

FIFO with CRC in a PLD

An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.

Content-addressable memory with cascaded match, read and write logic in a programmable logic device

Cascadable bus based crossbar switch in a programmable logic device

A device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second signal interface. A second programmable logic device may be configured to have (i) a third signal interface and (ii) a fourth signal interface. The assembly apparatus is generally configured to (i) mount the first programmable logic device and (ii) mount the second programmable logic device. A first external contact may be connected to the first signal interface. A second external contact may be connected to the fourth signal interface. A direct connection may be provided between the second signal interface and the third signal interface.

Architecture for implementing two chips in a package

A method of fabricating a semiconductor package that may contain two or more dies. The method generally comprises the steps of (A) mounting a first die having a first side on an assembly apparatus and (B) mounting a second die having a second side and an adjoining third side on said assembly apparatus. The second die may be oriented such that (i) the second side and the third side both face the first side and (ii) the second side and the third side are both substantially nonparallel to the first side.

Method of placing die to minimize die-to-die routing complexity on a substrate

A test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester may be configured to (i) stimulate the first function with a test signal to present a first output signal, (ii) stimulate the final function with the first output signal to present a final output signal; (iii) measure a result between the test signal and the final output signal, and (iv) allocate the result between the first function and the final function to disperse a measurement error in the result.

Tester accuracy using multiple passes

A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to (i) implement user defined programmable logic and (ii) generate an output in response to a first input and a second input. The second circuit may be configured to generate the second input in response to the output, a third input, and a fourth input.

Multiplexers for efficient PLD logic blocks

A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits. Using redundancy to correct errors caused by charge loss or charge gain within previously stored product engineering values proves a beneficial outcome since testing the product engineering bit locations is not necessarily a viable solution. The product engineering bit locations may be programmed well before test patterns can be written to and read from those locations. Further, the uniquely programmed product engineering bits may unduly be lost during normal assembly of die into an integrated circuit package.

Method, circuit and apparatus for preserving and/or correcting product engineering information

A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output in response to a first input, a second input and a third input. The second circuit may be configured to generate a second output and a third output in response to a fourth input and a fifth input. The second output may be coupled to the second input and the first output may be coupled to the fifth input.

A programmable logic device comprising a first plurality of logic blocks each comprising a first number of I/O macrocells, a second plurality of logic blocks each comprising a second number of I/O macrocells and a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks.

Heterogeneous CPLD logic blocks

A logic block in a product-term based programmable device comprising a first logic gate, a second logic gate, a macrocell and a multiplexer. The first logic gate may be configured to generate a first output in response to a logical combination of a first number of product terms. The second logic gate may be configured to generate a second output in response to a logical combination of a second number of product terms. The macrocell may be configured to generate a third output in response to the second output. The multiplexer may be configured to select an output of the device in response to (i) the first output or (ii) the third output. The first number of product terms may be a subset of the second number of product terms.

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Pleasanton, CA, United States of America

Christopher W Jones