Arm Limited

Christopher Vincent Severino

Dominic William Brown

Ashley John Crawford

Seow Chuan Lim

Gergely Kiss

Csaba Kelemen

Andrew Brookfield Swaine

John Michael Horley

Tessil Thomas

Matthew Lucien Evans

Kar-Lik Kasim Wong

Richard Andrew Paterson

Joseph Samuel Herd

Peter Czakó

Patrick Michael Overs

Aris Doros Aristodemou

A data processing apparatus includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus-2. The mapping parameters may be fixed or software programmable.

Power control circuitry for controlling power domains

There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

Address space access control

Aspects of the present disclosure relate to power bridge circuitry comprising a first interface configured to interface with a source power domain; a second interface configured to interface with a target power domain; transition circuitry to receive a transition indication that the power bridge circuitry is to transition to an idle state; communication circuitry to communicate messages between the interfaces; and message identification circuitry to identify messages communicated by the communication circuitry, the identification circuitry being configured to detect the communication of a given message directed to a target component connected to the second interface and indicating cessation of communication between the target component and a source component connected to the first interface. The transition circuitry is configured, responsive to receiving the transition indication and responsive to the message identification circuitry detecting communication of the given message, to initiate a transition of the power bridge circuitry to the idle state.

Methods and apparatus for interfacing between power domains

An apparatus has a control domain comprising functional circuitry to perform logical operations when in an operational state. The functional circuitry comprises at least one output and a state of the output depends on the logical operations. Domain control circuitry controls the control domain to put the functional circuitry in one of the operational state and a non-operational state. Isolation circuitry isolates the functional circuitry within the apparatus by holding the state of the output at a predetermined value when the domain control circuitry puts the functional circuitry in the non-operational state. Self-test control circuitry causes the domain control circuitry to control the control domain to put the functional circuitry in the non-operational state and to cause a self-test procedure to be carried out with respect to the functional circuitry.

Built-in self-test in a data processing apparatus

An integrated circuit and method are provided for managing power domains. The integrated circuit has first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state. Further, the additional power control circuitry is arranged to output a mode status signal that is then used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain. This ensures that, despite the power control circuitry losing knowledge of the current power state of the first power domain whilst it is in the power saving state, no unintended consequences occur when the second power domain subsequently exits the power saving state.

Technique for managing power domains in an integrated circuit

A data processing apparatus has a number of devices having a normal state and a quiescent state in which the device is ready for being placed in a power saving state. Each device provides at least one preference indication indicative of a preference to operate in the normal state or the quiescent state. A controller controls a common state transition process for transitioning each of the devicesbetween the normal state and the quiescent state based on the preference indication received from each device.

Controlling transitions of devices between normal state and quiescent state

An integrated circuit () has first and second domains (). The first domain has a power controller () to control the power state of at least one device () in the second domain based on power management signals exchanged on a power management channel () between the first and second domains A reset isolation bridge () is provided on the power management channel () between the first and second domains (). The bridge () has first and second interfaces () to exchange the power management signals with the first and second domains respectively. Isolating circuitry () is provided in the bridge () to respond to a reset indication () indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces () from each other.

Reset isolation bridge

A data processing apparatus () has a number of devices () having a normal state and a quiescent state. Transition sequencing circuitry () controls a sequential state transition process for transitioning each of the devices () in turn between the normal state and the quiescent state. For each device, the transition sequencing circuitry () controls the transition based on at least one preference indication transmitted from that device () providing an indication of a preference to operating the normal state or the quiescent state.

An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is currently ready to receive the data item.

Interface apparatus and method

Various implementations described herein are directed to a method and apparatus for a low power interface combiner for controlling a cross domain component in a system of two or more power domain controls. The combiner may include a first state for requesting cross domain component quiescence when a first control requests quiescence and a second state for ensuring cross domain component quiescence before accepting the first control quiescence request. The combiner may include a third state for requesting cross domain component quiescence exit when a last control requests quiescence exit and other controls have exited or are exiting quiescence. The combiner may include a fourth state for ensuring cross domain component quiescence exit before accepting the last control quiescence exit request.

Combination of control interfaces for multiple communicating domains

A system, apparatus and method for gathering monitoring data relating to the operation of a data processing system are disclosed. The data processing system comprises a monitor controller and a plurality of monitors which gather monitoring data relating to the operation of the data processing system. Each monitor does not send its monitoring data to the monitor controller unsolicited, but merely indicates to the monitor controller that it has such data ready for transmission. In response to reception of a data ready signal from more than one monitor, the monitor controller selects one of these monitors and sends it a data transmission command, thereby avoiding resource contention in a shared resource between data transmissions from more than one monitor.

Gathering monitoring data relating to the operation of a data processing system

An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. A system power controller controls operation of the component power control circuitry by setting a power mode lock condition therein. When the power mode lock condition is met the component power control circuitry cannot change the selected power mode of the component. Power control over the component is thus partially delegated from the system power controller to the component power control circuitry.

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Haverhill, United Kingdom

Christopher Vincent Severino