Altera Corporation

Xilinx, Inc.

Christopher Thomas Moore

Simardeep Maangat

Bo Zhou

Rajiv Dattatraya Kane

Systems and methods related to phase-locked loops circuitry and lock-detect circuitry are provided. Some of the systems and methods allow sharing of lock-detect circuitries between multiple phase-locked loops or other suitable circuitry. Others allow multiple circuitries to select from multiple lock-detect circuitries that may use different lock-detect techniques.

Systems and methods for sharing multiple lock-detect circuitries or multiple phase locked loop blocks

A circuit includes first and second signal networks, a driver circuit, and a bypass circuit. The driver circuit generates a first signal based on a second signal during a normal mode. The second signal is received from the first signal network. The bypass circuit is coupled to the driver circuit to provide a third signal generated based on the first signal to the second signal network during the normal mode. The bypass circuit receives a fourth signal from the first signal network during a test mode. The bypass circuit generates a fifth signal based on the fourth signal. The fifth signal is provided to the second signal network during the test mode. The bypass circuit prevents the driver circuit from driving a signal to the second signal network during the test mode.

Techniques for bypassing circuits during tests

A scan element with self scan-mode toggle is described. In an example, the scan element is configured to automatically switch between a capture mode and a scan mode. In the capture mode, data is captured from logic under test. In the scan mode, the captured data is scanned out for testing. The scan elements each include a shift register that serves a dual purpose of providing control for determining when the scan element is to switch from the capture mode and the scan mode, as well as providing a location to store captured data.

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Saratoga, CA, United States of America

Christopher Thomas Moore