Nvidia Corporation

Samsung Electronics Co., Ltd.

Pasternak Solutions, LLC

Christopher Thomas Cheng

Stephen C Purcell

Santosh Abraham

Liangjun Zhang

Ki Fung Chow

Shirish C Gadre

John Wakefield Brothers

Stephen Donald Lew

Thomas Edward Dewey

Karthik Ramani

Abhinav Golas

Ashish Karandikar

David Wyatt

John Stephen Montrym

Steven E Molnar

Emmett Michael Kilgariff

Abraham Benjamin De Waal

Gary M Tarolli

Brian D Hutsell

Sau Yan Keith Li

Franciscus W Sijstermans

David Matthew Stears

Wojciech Jablonski

Paul Martin Springer

Jonathan Edward Barker

Apparatuses, systems, and techniques to optimize kernel selection for performing a computation. In at least one embodiment, a neural network is trained and utilized to generate a list of kernels so that an (e.g., optimal) kernel may be identified. The neural network receives characteristics of the input matrices and determines relevancy scores for a list of possible kernels. Based on an ordered listing of kernels by relevant score, a kernel is selected from the list and utilized to perform the computation and provide the result.

Selecting computational kernel variants using neural networks

Embodiments of the present invention may be directed to a graphics system of a computer system. The system may include a frame buffer having a number of partitions respectively mapped to a number of discrete memory devices and a dedicated copy buffer operable to store new image frames, mapped to a first memory device. The first memory device corresponds to a first partition of the number of partitions. The system may also include a loader circuit coupled between the frame buffer and the dedicated copy buffer, operable to copy new image frames from the frame buffer to the dedicated copy buffer. The system may also include a clocked output coupled to receive an image frame from the dedicated copy buffer and operable to drive a display device therewith. The system may enter a low power state wherein a number of the discrete memory devices are powered off.

System and method for frame buffer copy during partial power down of memory

An apparatus, system and method is provided to determine a motion of pixels in local regions of a scene, classify the motion into a speed category, and make decisions on how to render blocks of pixels. In one implementation the motion in a tile is classified into at least three different speed regimes. If the pixels in a tile are in a quasi-static speed regime, a determination is made whether or not to reuse a fraction of pixels from the previous frame. If the pixels are determined to be in a high speed regime, a decision is made whether or not a sampling rate may be reduced.

Motion based adaptive rendering

In a graphics system regions of a frame are analyzed to determine local regions of the frame in which adaptive desampling may be performed. In one implementation a standard sampling scheme includes at least one sample per pixel and regions that are adaptively desampled have one sample for a block of pixels having a size of at least four pixels. A level of detail map is generating to identify regions in which desampling may be performed. The level of detail map may be based on detecting motion, detecting an edge, and detecting a content frequency.

Adaptive desampling in a graphics system with composited level of detail map

A method and apparatus for performing display image refresh in bursts to a display device. A buffered refresh controller includes capabilities to drive the display based on video signals generated from a local frame buffer at a first rate. The graphics controller may optimally be configured to burst a new frame of pixel data to the buffered refresh controller at a second rate to replace the previous frame of pixel data in the local frame buffer. The second rate is different than the first rate. Additionally, the graphics controller may send frames only when they contain new pixel data. By enabling the graphics controller to selectively transmit the new frame of pixel data at the second rate, higher than the first rate, the graphics controller may be placed in a power-saving state during at least a portion of each frame update.

Method and apparatus for performing burst refresh of a self-refreshing display device

A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Video processor having scalar and vector components

A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Multidimensional datapath processing in a video processor

Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path between the multiple processors and shared memories is provided by a multi-stage crossbar network comprising a plurality of serially interconnected crossbar switches, wherein each of the crossbar switches independently assigns local memory transaction identifiers to each memory transaction request that it processes and uses the local memory transaction identifiers to match each received memory transaction result with its corresponding previously processed memory transaction request.

Layered crossbar for interconnection of multiple processors and shared memories

A system and method for providing antialiased memory access includes receiving a request to access a memory address. The memory address is examined to determine if the memory address is within a virtual frame buffer. If the memory address is within a virtual frame buffer then the memory address is transformed into one or more physical addresses within a frame buffer that is utilized for antialiasing. The frame buffer may be a single memory space containing subpixel information corresponding to pixels of the virtual frame buffer. Subpixels located at the physical addresses within the frame buffer are then accessed. The disclosed invention provides for direct access by a software application.

Transparent antialiased memory access

Embodiments of the present invention recite a method and system for accessing data. In one embodiment of the present invention, a plurality of instances of data are stored in a memory device which comprises a plurality of memory modules disposed as an array of parallel columns. In response to receiving an indication that said plurality of instances of data is being accessed as a row of data, a first address translation table is accessed which describes the same row address in each of said plurality of memory modules wherein an instance of data is stored. Then, in response to receiving an indication that said plurality of instances of data is being accessed as a column of data, a second address translation table is accessed which describes a successive row address in each successive memory module wherein an instance of data is stored.

Method and system for implementing low overhead memory access in transpose operations

A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Growing community of inventors

Santa Clara, CA, United States of America

Christopher Thomas Cheng