Src Corporation

Christopher Thomas Capraro

Mark D Barnell

Jason Michael Steeger

Darrek J Isereau

Eva Beth Piltch

Methods and systems for scalable high-performance embedded computing architectures. According to an embodiment, a scalable high-performance embedded computing system increases computational capability within the restrictive size, weight, and power constraints of systems such as the external pod payloads of unmanned aircraft systems, among many other possible systems. The core computer capability can be placed in various environments, and according to one embodiment utilizes a flight-certified aeronautics pod that is scalable in length. The scalable HPEC system can be connected to external data sources, or the nose and tail can be made of Radio Frequency transparent material, enabling the use of various RF sensing technologies within the same aeronautics enclosure. According to an embodiment, a lightweight, thermally-efficient conduction cooled chassis supports the required board and interface hardware.

Scalable high-performance embedded computing systems

A radar system includes an image forming circuit that provides a two-dimensional image of an operating environment. The image includes pixel elements representative of the operating environment. The system includes at least one filter configured to convert the two-dimensional image into a clutter classification map of clutter regions. A predetermined number of clutter regions are selected as training cells for a predetermined cell-under-test (CUT). A space-time adaptive processor (STAP) is configured to derive a weighted filter from training cell data. The STAP applies the weighted filter to a digital return signal associated with the predetermined CUT to provide a STAP-filtered digital return signal having the clutter signal components substantially eliminated therefrom.

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Utica, NY, United States of America

Christopher Thomas Capraro