Smsc Holdings Sarl

Motorola Corporation

Symwave, Inc.

Christopher T Thomas

Mahibur Rahman

Clinton C Powell, Ii

Jun Ye

Wei Fu

Edgar Herbert Callaway, Jr

Chun-Ye Susan Chang

Robert K Schweickert

Yanggao Qiu

Qing Li

James G Mittel

Hongming An

James David Hughes

Yossi Cohen

CongQing Xiong

Junling Zang

Yuping Luo

Octavian Popescu

James A Kimball

Xia Lei

Yao Zhigang

Qiu Yang

Systems and methods are provided to calibrate and compensate for signal impairments from the use of cables in data communication devices. Signal impairments such as intra-pair skew of differential signals and frequency dependent insertion loss are measured during a calibration phase. One end of the cable is connected to a communication device. The other end of the cable is configured to loop back calibration signals transmitted from the communication device. The calibration signals looped back from the communication device are received and measured by the communication device. The measured impairments are used to determine transmit and receive impairment compensation settings to compensate for impairments caused by the cable. These settings are stored and used to adjust signals transmitted from the communication device to compensate for the transmit impairment. These setting are also used to adjust signals received by the communication device to compensate for the receive impairment.

Internal cable calibration and compensation

Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.

System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios

Various techniques are provided to facilitate the identification of devices, such as high performance data communication devices, when such devices are connected over a data communication bus. In one example, high performance devices may identify each other by providing frequency modulated signal bursts which fall within a range of frequencies associated with a data communication standard. Similarly-implemented high performance devices may recognize patterns encoded in the frequency modulations of the signal bursts and thereby identify each other. Advantageously, while providing the frequency modulated signal bursts, the high performance devices may remain compliant with the data communication standard to facilitate communication with other types of devices which may expect to receive communications in accordance with the data communication standard.

Device identification using frequency modulated signal bursts

Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is asynchronous to the transmitter clock used to transmit the received data stream. In one example, the received data stream is oversampled using N evenly-spaced multi-phase clocks. The oversampled data are packed into a data block. Data transition edges of the oversampled data in the data blocks with respect to multi-phase clocks are tracked. The tracked data transition edges are used to determine the length of a decision window and to further divide the oversampled data into groups of bits that are hypothesized to be samples of the same received data symbol. Bit mapping is performed on the decision window to recover the received data symbol. By tracking the movement of data transition edges, the technique enhances data recovery capability.

Systems and methods for high speed data recovery with free running sampling clock

Various techniques are provided for hosting storage media devices using multi-port devices having a plurality of ports. For example, in one embodiment, a method of operating a multi-port device includes detecting whether a host device or a storage media device is connected to a first port of the multi-port device or a second port of the multi-port device. The method also includes, if the host device is connected to the first port, configuring the first port as a slave port and operating the multi-port device as a slave hosted by the host device. The method also includes, if the host device is connected to the second port and the storage media device is connected to the first port, configuring the first port as a host port and hosting the storage media device from the multi-port device.

Multi-port device with controller for storage media device port

Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to transmit and receive data to and from a host device in accordance with a first protocol. A synchronous second interface is adapted to transmit and receive data to and from a device external to the host device in accordance with a second protocol. A bridge controller is adapted to convert the data received from the host device from the first protocol to the second protocol for transmission to the external device. A clock and data recovery (CDR) block is adapted to recover a clock signal from the first interface to synchronize the data received from the host device. The second interface is adapted to synchronize the converted second protocol data transmitted to the external device using the recovered clock signal.

Clocking scheme for bridge system

Various techniques are provided for selectively allocating a buffer adapted to be shared for storage media device data communications and downstream device data communications routed through a hub. For example, in one embodiment, a method includes detecting if one or more downstream devices are connected to one or more downstream device ports of the hub. The method also includes, if any downstream devices are detected: allocating a first portion of the buffer for a storage media device controller, allocating one or more second portions of the buffer for the detected downstream devices, wherein each of the second portions is associated with a corresponding one of the detected downstream devices, and passing the storage media device data communications between a host device and the storage media device controller through the first portion of the buffer and not the second portions of the buffer.

Shared buffer for data communications routed through hub

Systems and methods are provided to permit indirect measurements of sample time errors using multiphase interpolator clocks generated from a local reference clock in clock recovery blocks of high speed data receivers. The multiphase interpolator clocks are adjusted to have substantially evenly spaced phase offsets within a data period of the local reference clock. A small frequency offset between the transmitter clock and the local reference clock causes transition edges of received data to drift slowly across the interpolated clocks. Differences in phase offsets between the interpolated clocks may be determined with high resolution by counting the number of data transitions occurring between pairs of interpolated clocks over a long period of time. Phase offsets are adjusted to make the data transition counts substantially the same for the interpolated clocks. Data recovery may then be facilitated by selecting an interpolated clock with a sampling edge that is closest to the center of a data period to sample the received data.

Sample time correction for multiphase clocks

Systems and methods are disclosed for improving the accuracy of phase spacing of multiphase clocks. In one example, method includes receiving a reference clock having a first frequency and sampling the reference clock with a plurality of multiphase clocks having a second frequency to generate a plurality of samples. The second frequency is a non-integer multiple of the first frequency. The method also includes detecting transitions of the reference clock occurring between the samples generated from a plurality of pairs of the multiphase clocks and counting the transitions to generate a transition count for each pair of the multiphase clocks. The method also includes summing a set of the transition counts to generate a measured phase for a first multiphase clock, calculating a reference phase for the first multiphase clock, and generating a phase skew value for the first multiphase clock based on the measured phase and the reference phase.

Multiphase clock generation and calibration

Various techniques are provided for interfacing external devices with host computer systems. In one example, hard drive parameters may be retrieved from a nonvolatile memory of an external hard drive enclosure device in order to register the external device with a host device while the host device provides a low power level to the external device. Following registration of the external device, the host device may provide a high power level to the external device to operate the registered external device. The hard drive parameters may be stored in the nonvolatile memory by a provider of the external device. In another example, the hard drive parameters may be loaded into the nonvolatile memory by appropriate software running on the host device. In yet another example, the external device may read the hard drive parameters from the hard drive while emulating another external device.

Methods and systems for interfacing bus powered devices with host devices providing limited power levels

A fingerprint sensor interface that connects to a standard camera interface and minimizes input and output signals to reduce sensor die area and cost. The sensor can connect to a standard camera interface of a cellular telephone baseband processor or other device intended to receive signals from a camera. Input and output pad are arranged on a single edge of the die. Circuitry between the pads and the sensor active array creates clearance from the array to the bond wires connected to the pads.

Fingerprint sensor and interface

A fingerprint imager uses a non-rectangular image readout to reduce the bandwidth and data size of the read-out image. Narrow-width rows in the central portion of the image are used to align successive partial image frames of the fingerprint to reconstruct a full image of the fingerprint using full-width rows of the fingerprint frames.

Fingerprint sensor and method of transmitting a sensor image to reduce data size and data rate

A Flash-interfaced Fingerprint Sensor is disclosed. The sensor device interfaces directly with a flash memory interface chip. The flash memory interface chip incorporates the system for interfacing with flash memory devices, a fingerprint sensor/detector system, and an encryption subsystem for encrypting data being passed to and from the flash memory devices and the host computing device. The device further employs an advanced encryption approach that entails fingerprint decryption and verification on the host computer rather than on the portable memory apparatus. Once verification at the host computer is complete, memory and host functionality is enabled.

Flash-interfaced fingerprint sensor

A Video and Audio Front End Assembly and Method. The device and method of this invention takes advantage of the hardware improvements available in personal computing machines that enable higher speed bus communications and much greater computational capacity. The system converts many of the processes needed to convert analog video and audio inputs so that they are displayable by a personal computer from a hardware integrated circuit to a set of software routines. The system combines a simplified hardware front-end interface between the computer and the analog input signals and a very flexible set of software applications running on the host computer. The hardware front end employs an integrated circuit device that is much lower in complexity and cost than the conventional audio/video decoder integrated circuit. The software back end provides performance that is equal to the prior hardware-based systems, while also having the substantial benefit of being upgradable at virtually no cost to respond to changing user requirements and technological evolutions in the decoding arena.

Video and audio front end assembly and method

A correlation demodulator unit () having gain normalization includes a correlation demodulator () for receiving a signal from a receiver (). The correlation demodulator has a plurality of correlators (C-C) corresponding to a plurality of N correlator outputs. A gain normalizer () is coupled to the correlation demodulator for accumulating symbol energy on a symbol by symbol basis for each of the plurality of correlator outputs based upon a current symbol decision providing at least an accumulated value within an accumulator () for the plurality of correlators and for normalizing the plurality of N correlator outputs using the accumulated value(s).

Growing community of inventors

Fort Lauderdale, FL, United States of America

Christopher T Thomas