Texas Instruments Corporation

Christopher T Maxwell

Aline Claude Sadate

Nakshatra S Gajbhiye

James Craig Spurlin

John Mitchell Perry

Mustapha El-Markhi

Conventionally, current detection in load switches is implemented by monitoring the voltage across a small value sense resistor in series with the load switch, where the differential voltage across is applied to a comparator to generate a control signal corresponding to a light load condition, a normal load condition, or an over-load condition. Detecting the light load condition, however, can be difficult to determine using this arrangement due to the low differential voltage. Here, however, a integrated circuit (IC) is provided that employs an internal voltage supply and comparators to examine the load current to determine whether a light load condition is present, which does not suffer from the same problems.

Load switch having load detection

Load switches are relatively common and in use with a variety of applications, and conventional load switches have been designed to have continually operating protection circuitry, which can consume a great deal of power. Here, a load switch integrated circuit (IC) is provided where a controller within the IC activates and deactivates various protection circuits in a sequence, allowing the protection circuit to protect the IC while also reducing power consumption.

Low power load switch with protection circuitry

A power efficiency control circuit eliminates short circuit power consumption associated with a CMOS output buffer in a manner that substantially increases the buffer operating efficiency. The technique is implemented to allow for a reduction of power associated with the output buffer pre-driver stage. The methodology employs a power efficiency control circuit that tri-states the output buffer before every transition.

Power efficiency control output buffer

An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level. A control circuit is responsive to the output of the control circuit to control the voltage at the gates of the second pull-up transistor and the second pull-down transistor to provide the logic level at the output node only when the output of the control circuit indicates when the supply voltage is below the predetermined level.

Growing community of inventors

Sherman, TX, United States of America

Christopher T Maxwell