International Business Machines Corporation

Globalfoundries Inc.

Elpis Technologies Inc.

Christopher Stephen Putnam

Robert J Gauthier, Jr

Souvick Mitra

JunJun Li

Tom C Lee

Michel J Abou-Khalil

Mahmoud A Mousa

James Paul Di Sarro

Robert Russell Robison

Junjun Li

Kiran V Chatty

Ning Lu

Mujahid Muhammad

Eric Thompson

Terence B Hook

Robert Allen Groves

Edward J Nowak

Anthony K Stamper

Theodorus E Standaert

William R Tonti

Andres Bryant

Mark David Jaffe

Chengwen Pei

Matthew Joseph Breitwisch

John Joseph Pekarik

Randy William Mann

William F Clark, Jr

Jeffrey Scott Brown

David Michael Fried

Hongmei Li

Michael J Abou-Khalil

Mohammad I Younus

Jed Hickory Rankin

Arne Watson Ballantine

James William Adkisson

Shreesh Narasimha

Anthony I Chou

James Stuart Dunn

Roger Allen Booth, Jr

Paul David Agnello

BethAnn Rainey

John P Connor

Christopher M Schnabel

Alan L Roberts

Robert Gauthier

Brian M Dufrene

Christopher H Lumbra

Mitra Souvick

Dimitrios K Kontos

Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.

Structures and methods for RF de-embedding

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Structures, methods and applications for electrical pulse anneal processes

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

SCR with fin body regions for ESD protection

Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

Electrostatic discharge protection circuit with a fail-safe mechanism

Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Through silicon via repair

Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction.

Dual three-dimensional (3D) resistor and methods of forming

Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.

Silicon controlled rectifier with integral deep trench capacitor

Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

Bulk FinFET ESD devices

A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure.

Interdigitated vertical native capacitor

Growing community of inventors

Hinesburg, VT, United States of America

Christopher Stephen Putnam