Oracle America, Inc.

Sun Microsystems, Inc.

Netapp, Inc.

Philo, Inc.

Christopher Small

Alexandra Fedorova

Daniel Nussbaum

James F Lentini

Christopher A Thorpe

Stephen Michael Byan

Thomer Gil

The system provides a method and apparatus for writing a unique copy of data associated with each of a plurality of individual users, without the need for storing duplicate copies of the entire data file. The system provides for creating an unusable copy of a portion of the data that is to be shared by all users of the complete data. The system will store and optionally encrypt and/or watermark a unique copy of the remainder portion of the data for each unique user. When accessed from storage, the system will combine the shared portion with the unique remainder to reconstitute the entire file for access by the user. Deleting the unique remainder associated with a particular user makes all of the data useless to that user. In one embodiment, the system first compresses the entire data file using index frames and delta.

Method and apparatus for video compression of multiple instances using index frames

Systems and methods for efficiently using solid-state devices are provided. Some embodiments provide for a data processing system that uses a non-volatile solid-state device as a circular log, with the goal of aligning data access patterns to the underlying, hidden device implementation, in order to maximize performance. In addition, metadata can be interspersed with data in order to align data access patterns to the underlying device implementation. Multiple input/output (I/O) buffers can also be used to pipeline insertions of metadata and data into a linear log. The observed queuing behavior of the multiple I/O buffers can be used to determine when the utilization of the storage device is approaching saturation (e.g., in order to predict excessively-long response times). Then, the I/O load on the storage device may be shed when utilization approaches saturation. As a result, the overall response time of the system is improved.

Specializing I/O access patterns for flash storage

A thread scheduling technique for assigning multiple threads on a single integrated circuit is dependent on the CPIs of the threads. The technique attempts to balance, to the extent possible, the loads among the processing cores by assigning threads of relatively long-latency (low CPIs) with threads of relatively short-latency (high CPIs) to the same processing core.

Thread scheduling in chip multithreading processors

A computer system includes an integrated circuit that has a plurality of processing cores fabricated therein and configured to perform operations in parallel. Each processing core is configured to process multiple threads, where a thread is assigned to one of the plurality of processing cores dependent on a cache hit rate of the thread.

A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

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Cambridge, MA, United States of America

Christopher Small