Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Christopher Shawn Kroeger

David R Maciorowski

Derek Alan Sherlock

Michael S Allison

Michael John Erickson

Shawn Kenneth Walker

Edward A Cross

A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

Mapping entry invalidation

Examples herein disclose an identification of a set of skew requirements corresponding to a set of data signals. Based on the set of skew requirements, the examples prioritize an order of transmission for the set of data signals. The example queue the set of data signals in accordance with the prioritized order.

Prioritization for a set of data signals based on skew requirements

Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board.

Distributed joint test access group test bus controller architecture

The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and stored on a firmware server. The programmable parts are preferably integrated with the printed circuit boards; each of the boards networks to the firmware server by connection with an interface server, such that the image files download to the circuit board for programming the board's internal programmable parts. Networking between the parts and the firmware server can include communications across the Internet and/or one or more area networks. Multiple interface servers may be integral with the products incorporating the programmable parts so that many products may be updated concurrently.

Method for just-in-time updating of programming parts

A system for providing notification, to the associated operating system, of removal and replacement of I/O devices during operation of a multiprocessor computer system running multiple operating systems. The system includes a plurality of cells, each containing multiple RISC processors, low-level I/O firmware, a local service processor, scratch RAM, external registers, a memory and I/O manager, and interfacing hardware. Each partition comprises one or more cells and runs its own operating system (OS). Each cell is connected to a peripheral backplane containing a plurality of peripheral I/O card slots via a switch on the system backplane, which also connects the cell to a supervisory processor, which sends card slot status information to the appropriate cell. Each I/O (typically PCI) card slot has an associated latch which provides an indication, to the supervisory processor, that a platform event has occurred. Platform events include inserting or removing an I/O (peripheral device interface) card to/from a card slot, and opening an access panel that provides access to the I/O cards.

Growing community of inventors

Longmont, CO, United States of America

Christopher Shawn Kroeger