Texas Instruments Corporation

Christopher Scott Whitesell

Abbas Ali

Henry Litzmann Edwards

John Christopher Shriner

Brian Keith Kirkpatrick

Mona M Eissa

Bradley David Sucher

Pushpa Mahalingam

Byron Joseph Palla

Corinne Ann Gagnet

James Hoyt Beatty

Joshua J Hubregsen

A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Control of locos structure thickness without a mask

A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

Gate oxide fabrication and system

Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Reduced semiconductor wafer bow and warpage

In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region.

Method of manufacturing a semiconductor device having improved transistor performance

Improved long gas injectors for a vertical furnace used in semiconductor wafer processing are useful to minimize particulate contamination in the wafer processing area of the furnace, and minimize distortion of the long injectors during thermal excursions. The improved injectors are fabricated with a stabilizing quartz standoff positioned near the onset of the vertical portion of the injector tube which adds support to the long tube. Thickness of the standoff is calculated to define and enforce a specified separation distance between liner and injector, as well as to provide dual alignment points at the base of the liner and at the tip of the injector.

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Garland, TX, United States of America

Christopher Scott Whitesell