Intel Corporation

Christopher Schaef

Vaibhav Vaidya

Suhwan Kim

Harish Krishnamurthy

Nachiket Venkappayya Desai

Vivek K De

Sriram R Vangal

Krishnan Ravichandran

Turbo Majumder

Xiaosen Liu

Khondker Z Ahmed

Lilly Huang

Tanay Karnik

William J Lambert

Kaladhar Radhakrishnan

Krishna Bharath

David Arditti Ilitzky

Ankit Prakash Gupta

Dileep J Kurian

Sriram Kabisthalam Muthukumar

Alexander Lyakhov

Juan Munoz Constantine

Adel A Elsherbini

Sriram Srinivasan

Sally Safwat Amin

Ilya Klochkov

Akhila M

Sergio Carlo

Ajay Janardanan

Tamir Salus

Alex Lyakhov

A microelectronic assembly is disclosed, comprising a first integrated circuit (IC) die having electrical load circuits, first control circuits, and a second control circuit, a second IC die having powertrain (PTR) phase circuits electrically coupled to the first IC die, and inductors in a package substrate electrically coupled to the first IC die and the second IC die within a package. Individual ones of the first control circuits regulates power to a corresponding one of the electrical load circuits. The second control circuit maps the first control circuits and the PTR phase circuits. The PTR phase circuits control power to the inductors. The first control circuits, the second control circuit, the PTR phase circuits and the inductors together function as a voltage regulator configured to receive power from the package substrate at a first voltage and deliver power to the electrical load circuits at a second voltage.

Configurable multi-domain multi-phase disaggregated voltage regulator

Embodiments herein relate to identifying, by phase current balancing (PCB) circuitry, an indication of whether a measured current of a pulse-width modulated (PWM) signal of a plurality of PWM signals is greater than or less than an average current of the plurality of PWM signals. Embodiments further relate to adjusting, by the PCB circuitry, a bias-value of a non-modulated edge of a duty cycle of the PWM signal. Other embodiments may be described and claimed.

Current-balance control

Embodiments herein relate to a circuit which generates a sawtooth waveform based on an adaptive feedback loop that self-corrects the ramp up rate to account for variations in a device. The sawtooth waveform is obtained by repeatedly charging and discharging a capacitor according to a clock signal. The sawtooth waveform can be sampled once per clock period at a comparator which provides a corresponding binary output to a state machine. If the binary output indicates the amplitude of the sawtooth waveform is below a desired maximum voltage, the state machine outputs a code word to a digitally-controlled variable current source to increase the output current. The sawtooth waveform can be used to provide a pulse-width modulated (PWM) waveform such as for a DC-DC converter.

Digitally calibrated sawtooth generator for PWM based buck converters

A microelectronic assembly is provided comprising a first integrated circuit (IC) die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR), and a third IC die comprising inductors of the VR. The third IC die is between the first IC die and the second IC die, and the VR receives power at a first voltage and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the inductors in the third IC die comprise magnetic thin films. The third IC die may be a passive die without any active elements in some embodiments. In some embodiments, the microelectronic assembly further comprises a package substrate having conductive pathways, and the second IC die is between the third IC die and the package substrate.

Packaging architecture for disaggregated integrated voltage regulators

Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

Multi-phase switching regulators with hybrid inductors and per phase frequency control

Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

Multiple output voltage conversion

A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

Fuse-less self-start controller

Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

Deriving power output from an energy harvester

In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.

Energy harvester with multiple-input multiple-output switched-capacitor (MIMOSC) circuitry

Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.

Early pre-charge enablement for peak power application in net zero energy devices

An embodiment of a harvester apparatus comprising two or more charge pump stages may include at least a first charge pump stage to receive an alternating current source, and a second charge pump stage coupled to the first charge pump stage.

Self-starting AC harvester

An apparatus has a comparator circuitry (e.g., auto-zero comparator) with a first input, a second input, a third input; and an output; a first device (e.g., a low-side switch) coupled to the first and second inputs of the comparator; and a circuitry (e.g., a self-tuning logic) to generate a digital code which represents a comparator offset adjustment with reference to detection of current through a second device (e.g., an inductor), wherein the digital code (e.g., a multibit digital signal) is provided to the third input of the comparator circuitry.

Self-tuning zero current detection circuit

Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.

Physically unclonable function implemented with spin orbit coupling based magnetic memory

In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.

Growing community of inventors

Hillsboro, OR, United States of America

Christopher Schaef