International Business Machines Corporation

Christopher Scerbo

Kevin K Chan

Sebastian Ulrich Engelmann

Hongwen Yan

Jeng-Bang Yau

Renee Tong Mo

Yu Zhu

Robert L Bruce

Marinus Johannes Petrus Hopstaken

A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

III-V extension by high temperature plasma doping

After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

Self-aligned trench metal-alloying for III-V nFETs

Growing community of inventors

Bronx, NY, United States of America

Christopher Scerbo