Apple Inc.

Advanced Micro Devices Corporation

Christopher S Thomas

Mridul Agarwal

James Nolan Hardage

Rohit Kumar

Eric C Quinnell

Rajat Goel

Christopher M Tsay

Harsha Krishnamurthy

Muthukumaravelu Velayoudame

Shyam Sundar Balasubramanian

Skanda K Srinivasa

A processor includes a processing pipeline, a plurality of result-storage elements, and writeback logic. The processing pipeline is configured to process program operations and to write, to a result storage, up to a predefined maximal number of results of the processed program operations per clock cycle. The result-storage elements are configured to store respective ones of the results. The writeback logic is configured to (i) detect a writeback conflict event in which the processing pipeline produces simultaneous results that exceed the predefined maximal number of results, for writing to the result storage, in a same clock cycle, (ii) in response to detecting the writeback conflict event, to temporarily store at least a given result, from among the simultaneous results, in a given result-storage element, and (iii) to subsequently write the temporarily-stored given result from the given result-storage element to the result storage.

Writeback hazard elimination using a plurality of temporary result-storage elements

In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.

Register allocation system

In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Register file circuit design process

Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a clock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

Coarse gating of clock tree elements

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Austin, TX, United States of America

Christopher S Thomas