Matrix Semiconductor, Inc.

Sandisk 3d LLC

Sandisk Technologies Inc.

Sandisk Corporation

Christopher S Moore

Roger March

Derek Bosch

J James Tringali

Daniel T Brown

Chia Yang

Daniel C Steere

Roy E Scheuerlein

James E Schneider

Samuel Yu

Adrian Jeday

Matt Fruin

Richard Matthew Fruin

Michael A Vyvoda

Ron Barzilai

David Russell Friedman

Colm P Lysaght

Jason S Whetstone

Hironaga Ino

James Montague Cleeves

Mark G Johnson

Alper Ilkbahar

Bendik Kleveland

Kyle Loudon

Richard Matt Fruin

These embodiments relate to authentication and securing of write-once, read-many (WORM) memory devices. In one embodiment, a memory device comprises a controller operable in first and second modes of operation after stored security information is validated, wherein in the first mode of operation, the memory device operates in a read-only mode, and wherein in the second mode of operation, the memory device operates in a write-once, read-many (WORM) mode. In another embodiment, the controller is operative to perform security methods.

Authentication and securing of write-once, read-many (WORM) memory devices

One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. These embodiments can also be used to prevent accidental or deliberate overwrites, changes, or deletions to existing data in a WORM memory device.

Method and memory device that powers-up in a read-only mode and is switchable to a read/write mode

Memory device operable in read-only and write-once, read-many (WORM) modes of operation

The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash&#x2014;an erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a viable way to bridge one-time or few-time programmable memories with existing consumer electronic devices that have flash card slots. These embodiments also allow future consumer electronic devices to be designed without updating firmware to include a file system customized for a one-time or few-time programmable memory.

Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable-rewriteable memory

A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N&#x2212;1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N&#x2212;1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N&#x2212;1, N, and N+1.

Method for repairing a neighborhood of rows in a memory array using a patch table

A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N&#x2212;1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N&#x2212;1, N, and N+1 to a table stored in the memory device.

Memory device for repairing a neighborhood of rows in a memory array using a patch table

Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory

Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewritable memory

A digital storage system is coupled to a write-once memory array. File delete commands are implemented by over-writing a destructive digital pattern to at least a portion of the memory cells associated with the file to be deleted. One disclosed system alters the manner in which a file delete command is implemented, depending upon whether the file is stored in a write-once memory or in a re-writable memory.

Method for deleting stored digital data from write-once memory device

The preferred embodiments described herein provide a method for reading data in a write-once memory device using a write-many file system. In one preferred embodiment, data traffic between a data storage device and a write-once memory device is redirected so that file system structures of a write-many file system do not overwrite previously-stored file system structures. Data traffic between the write-once storage device and a data reading device is also redirected so that a current file system structure of the write-many file system is provided to the data reading device instead of an out-of- date file system structure. In another preferred embodiment, a non-volatile write-many memory array is provided in the write-once memory device to store file system structures of a write-many file system. With these preferred embodiments, data stored during multiple sessions using a write-once file system can be read by a write-many file system, thereby increasing the memory device's interoperability among existing data reading devices. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Method for reading data in a write-once memory device using a write-many file system

The preferred embodiments described herein provide various data allocation and error recovery methods that allow data to be written to a write-once memory array using a write-many file system. Other preferred embodiments described herein relate to methods for generating a set of valid file system structures. The various preferred embodiments can be used alone or in combination with one another.

Method for storing data in a write-once memory array using a write-many file system

The preferred embodiments described herein provide a memory device and method for storing and reading a file system structure in a write-once memory array. In one preferred embodiment, a plurality of bits representing a file system structure is inverted and stored in a write-once memory array. When the inverted plurality of bits is read from the memory array, the bits are inverted to provide the file system structure bits in their original, non-inverted configuration. With this preferred embodiment, a file system structure can be updated to reflect data stored in the memory array after the file system structure was written. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Memory device and method for storing and reading a file system structure in a write-once memory array

The preferred embodiments described herein provide a memory device and method for storing and reading data in a write-once memory array. In one preferred embodiment, a plurality of bits representing data is inverted and stored in a write-once memory array. When the inverted plurality of bits is read from the memory array, the bits are inverted to provide the data in its original, non-inverted configuration. By storing data bits in an inverted form, the initial, un-programmed digital state of the memory array is redefined as the alternative, programmed digital state. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another. For example, the embodiments in which data bits are inverted can be used alone or in combination with the embodiments in which data is redirected.

Memory device and method for storing and reading data in a write-once memory array

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San Jose, CA, United States of America

Christopher S Moore