Emc Corporation

Christopher S MacLellan

John K Walton

Michael Bermingham

Almir D Davis

Jeffrey Kinne

Stephen Lawrence Scaringella

Kendell Alan Chilton

William F Baxter

Michael Sgrosso

Daniel Castel

Brian K Campbell

Robert A Thibault

Ofer Porat

Gregory S Robidoux

Paul C Wilson

John O'Shea

Rizwan Sheikh

Brian William Gallagher

William R Tuccio

Avinash Kallat

Nhut Tran

Mark Zani

Farouk Khan

Brian D Magnuson

Paul G Scharlach

Steven MacArthur

Kendall A Chilton

A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.

Method and system for arbitrating data transmissions

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Data storage system having plural data pipes

An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.

Method of and system for error checking in a data storage system

Data storage system having separate atomic operation/non-atomic operation paths

Protocol controller for a data storage system

A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

Method and system for detecting transmitter errors

A testing system (and method of using same) for testing a system-under-test (SUT) are provided. One embodiment of the testing system includes first, second, and third logic sections. The third logic section selectively couples either the first logic section or the second logic section to the SUT, based upon two control signals transmitted to the third logic section. One of the control signals is transmitted from a source external to the SUT, first logic section, second logic section, and third logic section. The other control signal is transmitted from the first logic section. When the third logic section couples the first logic section to the SUT, the first logic section may transmit one or more test-related signals to the SUT. When the third logic section couples the second logic section to the SUT, the second logic section may transmit one or more other signals to the SUT.

Testing system and method of using same

Low latency data transmission method and system

A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.

System having backplane performance capability selection logic

A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.

Split-FIFO multi-station data transfer system

A data processing system includes an input portion for receiving a digital word having N bits of data and M bits for error detection, a first error correction code generator for generating a first error correction code based on the N bits of data of the digital word and a second error correction code generator for generating a second error correction code based on the N bits of data of the digital word. A first logic operator performs a first logic operation on the first error correction code and the second error correction code to generate a data signature representative of a comparison of the first error correction code and the second error correction code and a second logic operator performs a second logic operation on the data signature and the M bits of the digital word to generate a constant signal representing a comparison of the data signature and the M bits of the digital word. A comparator compares the generated constant signal to a predetermined constant signal to determine if an error has occurred in at least one of the N bits of data in the digital word, the M bits of data in the digital word, the first error correction code and the second error correction code and an error signal generator generates an error signal indicating that an error has occurred in at least one of the N bits of data in the digital word, the M bits of data in the digital word, the first error correction code and the second error correction code if the generated constant signal is different from the predetermined constant signal.

Method of and system for validating an error correction code and parity information associated with a data word

A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources. The logic section inserts the indicia into a succeeding one of the locations of the buffers associated with such one of the processor providing such one of the requests. The logic section also simultaneously inserts such indicia into a next succeeding available location of the other ones of the plurality of buffers. The logic section inhibits execution of requests in the buffers stored in locations thereof succeeding the location having stored therein any such inserted indicia.

Multi-processor system having data coherency

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

Data storage system having point-to-point configuration

A method for determining Cyclic Redundancy Check (CRC) parity of data, such data comprising a plurality of bytes, each one of the bytes having a parity bit, the plurality of bytes of data having a CRC. The method includes generating the parity of the parity bits of the plurality of bytes of the data, such generated parity being the parity of the CRC of such data. The method includes: generating parity of the parity bits of the plurality of data bytes; and comparing such generated parity with the parity bit of the CRC of the data. The method receives data having a plurality of N bytes: [D(0), D(1), . . . , D(N&#x2212;1]) each byte having a parity bit p and computes the parity of [P(0), P(1), . . . P(N&#x2212;1)].

Cyclic redundancy check (CRC) parity check system and method

In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.

Growing community of inventors

Walpole, MA, United States of America

Christopher S MacLellan