Micron Technology Incorporated

Christopher S Hale

Kishore Kumar Muchherla

Sampath K Ratnam

Peter Sean Feeley

Ashutosh Malshe

Kevin Roy Brandt

Yun Li

Daniel J Hubbard

Marc S Hamilton

Michael G Miller

Renato C Padilla

Preston Allen Thomson

Scott Anthony Stoller

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Memory device with dynamic cache management

Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.

Memory devices and systems including static and dynamic caches, and related methods

A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.

Periodic flush in memory component that is using greedy garbage collection

System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid management units in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid management units on the memory device based on the amount of valid management units. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid management units.

Cache management based on memory device over-provisioning

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

Managing block retirement for temporary operational conditions

Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.

Memory device with dynamic storage mode control

System and methods are disclosed include a memory device and a processing device coupled to the memory device. The processing device can determine an amount of valid blocks in a memory device of a memory sub-system. The processing device can then determine a surplus amount of valid blocks on the memory device based on the amount of valid blocks. The processing device can then configure a size of a cache of the memory device based on the surplus amount of valid blocks.

Memory devices including a hybrid cache, methods of operating a memory device, and associated electronic systems including a memory device having a hybrid cache, are disclosed. The hybrid cache includes a dynamic cache that may include x-level cell (XLC) blocks of non-volatile memory cells, which may include multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., shared between the dynamic cache and a main memory. The hybrid cache includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache based on a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. The cache may be disabled based on, for example, program/erase (PE) cycles of one or more portions of the memory device or the workload exceeding a threshold, which may define one or more switch points. A method of operating a memory device may include writing data in the static cache if the static cache is available, and writing the data in the dynamic cache if the static cache is unavailable.

Memory devices and electronic systems having a hybrid cache including static and dynamic caches that may be selectively disabled based on cache workload or availability, and related methods

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Memory having a static cache and a dynamic cache

An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.

A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.

Growing community of inventors

Boise, ID, United States of America

Christopher S Hale