National Semiconductor Corporation

Christopher S Blair

Ali A Iranmanesh

Vida Ilderem

Alan G Solheim

Rick C Jerome

Madan Biswal

Rajeeva Lahri

George E Ganschow

Bancherd DeLong

Michael J Grubisich

Irfan Abdulqayyum Saadat

Abu-Hena Mostafa Kamal

Bamdad Bastani

James L Bouknight

Nick S Argenti

Tad Davies

Weidong Chen

Thomas S Crabb

Steve M Leibiger

A process for forming self-aligned cobalt silicide layers on an MOS transistor structure that reduces the risk of creating cobalt silicide bridges between source/drain regions and silicon (e.g. amorphous or polysilicon) gates. The process includes the use of an optimized argon sputter etch surface preparation step prior to cobalt layer deposition. The argon sputter etch step utilizes a DC bias of less than &minus;278 volts in order to insure that backsputtering of silicon onto gate sidewall spacers by the argon ions is minimized. Preferred argon etch sputter steps use a DC bias of less than &minus;80 volts, have a native silicon dioxide etch rate of no more than 5 angstroms per minute and target 20 to 60 angstroms of native silicon dioxide removal. Also provided is a process for preparing the surface of an MOS transistor or structure for subsequent cobalt layer deposition and cobalt salicide formation that includes use of an argon sputter etch process with a DC bias of less than &minus;278 volts.

Process for the formation of cobalt salicide layers employing a sputter etch surface preparation step

A process flow for forming a polysilicon-to-polysilicon capacitor performs the capacitor anneal step in a nitrous oxide ambient. As a result, a nitroxide layer forms over heavily doped polysilicon of the upper electrode of the capacitor. This nitroxide layer acts as a barrier against the diffusion of oxygen, preventing further oxidation of the heavily doped polysilicon electrode layer during the subsequent seal oxidation step. The nitroxide barrier layer is readily removed along with the other seal oxide layers immediately before formation of the silicided capacitor electrode contacts, without any attendant danger of overetching of gate oxide or spacer structures. Where the gate polysilicon layer is doped immediately after its formation, an additional capacitor anneal step in a nitrous oxide ambient is necessary to form an additional nitroxide layer.

Process for forming silicided capacitor utilizing oxidation barrier layer

A process for the controlled formation of self-aligned dual thickness cobalt silicide layers during the manufacturing of a semiconductor device that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, a semiconductor device structure (such as an MOS transistor) is first provided. The semiconductor device structure includes exposed silicon substrate surfaces (such as shallow drain and source regions) and a silicon layer structure disposed above the semiconductor substrate surface (such as a polysilicon gate). A cobalt layer is then deposited over the semiconductor device structure followed by the deposition of a titanium capping layer. Next, the thickness of the titanium capping layer above the silicon layer structure (e.g. a polysilicon gate) is selectively reduced using, for example, chemical mechanical polishing techniques. Cobalt from the cobalt layer is subsequently reacted with silicon from the exposed silicon substrate surfaces to form a first self-aligned cobalt silicide layer on these surfaces. At the same time, cobalt from the cobalt layer is reacted with silicon from the silicon layer structure to form a second self-aligned cobalt silicide layer thereon, which is thicker than the first self-aligned cobalt silicide layer.

Self-aligned dual thickness cobalt silicide layer formation process

A process for the controlled formation of dual thickness cobalt silicide layers on predetermined regions during the manufacturing of an integrated circuit that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, an integrated circuit (IC) structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A cobalt layer is then deposited over the IC structure, followed by the deposition of a titanium capping layer on the cobalt layer. The titanium capping layer is then pattered above predetermined regions of the IC structure. Cobalt in the cobalt layer that is in direct contact with silicon in the exposed silicon surfaces is subsequently reacted to form relatively thick cobalt silicide layers on the predetermined regions and relatively thin cobalt silicide layers elsewhere. The present invention also provides an IC structure with dual thickness cobalt silicide layers. The IC structure includes pluralities of first and second MOS transistor structures having source regions, drain regions and polysilicon gates. Relatively thin cobalt silicide layers are disposed on the first MOS transistor structures with shallow source and drain regions, while relatively thick cobalt silicide layers are disposed on the second MOS transistor structures with deep source and drain regions.

Integrated circuit structure with dual thickness cobalt silicide layers

A low contact resistance and low junction leakage metal interconnect contact structure for use with ICs. The contact structure includes an interconnect dielectric material layer on the surface of an IC semiconductor substrate. The interconnect dielectric material layer has a contact opening which extends to a predetermined region of the semiconductor substrate (e.g. a source region, drain region, or polysilicon gate layer). The contact structure also includes a cobalt (or nickel) silicide interface layer on the surface of the predetermined region that is aligned with the bottom of the contact opening, a cobalt (or nickel) adhesion layer on the sidewall surface of the contact opening, a refractory metal-based barrier layer on the metal adhesion layer and the metal silicide interface layer, and a conductive plug. Manufacturing process steps for such a contact structure include first providing a semiconductor substrate with at least one predetermined region (e.g. a drain region, source region or polysilicon gate layer), followed by depositing an interconnect dielectric material layer on the surface of the semiconductor substrate. Contact openings are formed through the interconnect dielectric material layer to expose the predetermined region. A cobalt (or nickel) adhesion layer is then deposited, followed by the deposition of a refractory metal-based barrier layer, and the reaction of cobalt (or nickel) from the adhesion layer with silicon from the exposed predetermined region to form a metal silicide interface layer. Finally, a conductive plug layer is deposited on the barrier layer, filling the contact opening.

Low contact resistance and low junction leakage metal interconnect

A merged single polysilicon bipolar NPN transistor, rather than using separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island. This significantly reduces device area because elimination of the second isolation island used in conventional designs reduces the N+ sink to NPN spacing. Buried layer and isolation layer processing proceed in the conventional manner. At sink mask, however, the mask is sized to uncover one end of the main device active region and a sink implant is performed. At base mask, the sink implant remains covered, rather than being exposed as in the conventional flow. At silicide exclusion, the oxide spacer layer is patterned to exclude silicide from the area above the sink implant region.

Merged single polysilicon bipolar NPN transistor

A polysilicon emitter of a bipolar device is formed utilizing a self-aligned Damascene technique. An oxide mask is patterned over epitaxial silicon implanted to form the intrinsic base. The oxide mask is then etched to form a window. Polysilicon is uniformly deposited over the oxide mask and into the window. The polysilicon is then polished to remove polysilicon outside of the window. Etching of the oxide mask follows, with good selectivity of oxide over silicon. This selectivity produces a polysilicon emitter atop an intrinsic base, the base flush with the silicon surface rather than recessed because of overetching associated with conventional processes.

Self aligned poly emitter bipolar technology using damascene technique

A method of forming a double polysilicon NPN transistor using a self-aligned process flow. The method includes use of a sacrificial oxide layer deposited over an epitaxial silicon layer prior to deposition and doping of the polysilicon layer from which the base electrode is formed. The sacrificial oxide layer acts as an etch stop for the plasma etch used to pattern the polysilicon layer. After patterning of the doped polysilicon layer, the sacrificial layer is removed using a wet etch. Etching of the oxide layer is performed in a manner which undercuts the doped polysilicon layer. Polysilicon is then deposited by a CVD process in the undercut region from which the initial polysilicon layer has been removed. The CVD deposited polysilicon fills in the gap between the doped polysilicon layer and the underlying epitaxial silicon layer caused by the oxide etch. The CVD deposited polysilicon is then oxidized. The portion of the CVD deposited polysilicon between the doped polysilicon layer and the single crystal silicon remains unoxidized. The oxidized CVD deposited polysilicon is then etched to form sidewall spacers. A second polysilicon layer is then deposited over the substrate and then implanted with an appropriate N+ type dopant. The transistor structure is then annealed to form junctions for the device.

Method of fabricating a self-aligned double polysilicon NPN transistor

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Method of fabricating BiCMOS device

A masking method for use in a silicide formation process is disclosed herein which prevents an oxide etching solution from tunneling under a photoresist masking layer and damaging oxide spacers not intended to be etched. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island. A mask opening used to etch exposed oxide spacer portions is made to not expose any parasitic oxide spacers formed along an edge of the isolated silicon island. In this way, an oxide etch solution is prevented from tunneling along the parasitic oxide spacer and reaching any intersecting oxide spacers not intended to be etched. The desired oxide spacers will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces.

Masking method used in salicide process for improved yield by preventing

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for submicron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

High performance semiconductor devices and their manufacture

A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

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San Jose, CA, United States of America

Christopher S Blair