Qualcomm Incorporated

Qualcomm Atheros Inc.

Atheros Technology Ltd.

Applied Micro Circuits Corporation

Christopher Rudolph Leon

Rabih Makarem

Kwai-Kwong K Lam

Lloyd Jian-Le Jiang

An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltage based upon an add signal and a subtract signal. A threshold generator generates a high threshold voltage and a low threshold voltage using and including at least one process dependent resistor and at least two temperature and process dependent current sources. The PLL responds during calibration to the control voltage being above the high threshold voltage by asserting the add signal directing the capacitor array to increase the capacitive load on the control voltage line, and to the control voltage being below the low threshold voltage by asserting the subtract signal to decrease the capacitive load.

Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated

A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources. A device in accordance with the present invention comprises a first frequency source, a second frequency source, a select signal, wherein the select signal is asynchronous with the first frequency source, and a multiplexer, which receives the first frequency source and the second frequency source, wherein the multiplexer selects as an output of the multiplexer one of the first frequency source and the second frequency source based on a value of the select signal, such that when the multiplexer switches between the first frequency source and the second frequency source, and between the second frequency source and the first frequency source, the transition is performed when the output of the multiplexer is at a logic low.

Glitchless clock multiplexer controlled by an asynchronous select signal

A voltage controlled oscillator having a temperature and process controlled output. A VCO in accordance with the present invention comprises a reference current source, a fixed current source, coupled in series with the reference current source, the fixed current source comprising a temperature independent current source, a third current source, coupled in parallel with the combination of the reference current source and the fixed current source, and an oscillator, coupled in series with the third current source, wherein a current used to control the oscillator is based on operating temperatures and processes of the reference current source and the third current source.

Voltage controlled oscillator open loop coarse amplitude control with respect to process and temperature variations

Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated circuit

A GPS receiver with automatic mode-setting and power ramping circuitry is disclosed. AGPS receiver in accordance with the present invention comprises a first switch network, comprising a plurality of transistors, a first plurality of circuit components, coupled to the first switch network, wherein the switch network selects paths through the circuit components to generate a Power On Signal (POS) and ramp power to the GPS receiver, a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver, a second plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver, and a second switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.

Automatic mode setting and power ramp compensator for system power on conditions

A tuned low-noise amplifier is disclosed. A device in accordance with the present invention comprises a first current source, a second current source, a comparator, coupled to the first current source and the second current source, for providing a control signal, and a third current source, receiving the control signal and coupled to the tuned low-noise amplifier, wherein a current in the third current source is proportional to a current in the first current source and the second current source, where values of the first current source, the second current source, and the third current source are based on a quasi-Proportional-To-Absolute-Temperature (PTAT) curve.

Automatic gain control and tuned low noise amplifier for process-independent gain systems

A differential latch circuit with a differential reset function includes a first arrangement of transistors configured to perform a latch function and a second arrangement of transistors, connected to the first arrangement of transistors, configured to perform a reset function. The first arrangement of transistors includes branches having three cascoded transistors, and the second arrangement of transistors includes branches having two cascoded transistors. This configuration enables the latch circuit to use lower power supply voltages relative to conventional latch circuits that require four more cascoded transistors.

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Irvine, CA, United States of America

Christopher Rudolph Leon