International Business Machines Corporation

Christopher Ro

Sebastian Theodore Ventrone

Stephen Dale Wyatt

Casey Jon Grant

Ahmed Y Ginawi

Bertrand Gabillard

Anjali R Malladi

Philippe Hauviller

Alexandre Maltere

Michael P Corriveau

A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal for a display between a plurality of signals, the system including: a microcontroller; a chooser for setting a primary signal from a plurality of program-variable signals; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition.

Structure for switching system for signal monitoring and switch-back control

Systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the system includes a microcontroller; a chooser for choosing a primary signal from a plurality of program-variable signals at the microcontroller; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition. A user can switch between signals such as television channels or other dedicated functions without the risk of missing a portion of the program material.

Switching system for signal monitoring and switch-back control

A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to 'lock' the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.

Sub-picosecond multiphase clock generator

There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Receiver having full signal path differential offset cancellation capabilities

An integrated circuit such as an application specific integrated circuit (ASIC) which has operational power supplies provided for different respective analog cores and digital logic and/or macros may be tested using on-chip power supplies, preferably comprising operational amplifiers connected as voltage followers and controlled by a band-gap voltage source or a voltage divider, drawing power from a single power supply to the chip which is generally provided in a standardized pin-out location. Disablement of respective operational amplifiers also provides electrical isolation of the respective cores during testing. A reduced pin-count is involved in the testing procedure since operational power supply connections can be open circuited or 'tri-stated'. On-chip power supplies for testing provides power while avoiding a need to provide low-noise power supplies and/or complex switching in a test system or to utilize custom front-end boards or both to provide power to arbitrary chip or package connections.

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Williston, VT, United States of America

Christopher Ro