International Business Machines Corporation

Christopher Raymond Conklin

William Vincent Huott

K Paul Muller

Kevin W Kark

Thomas J Knips

Randall W Philley

Luiz Carlos Alves

William J Clarke

Eric M Schwarz

Mark S Farrell

Charles Franklin Webb

Michael F Fee

Scott Barnett Swaney

Tobias Webel

Wen H Li

Andrew A Turner

Brenton F Belmar

Eberhard Engler

Walter Niklaus

Adolf Martens

Elliott Binder

Stephanie Lehrer

Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Tunable power save loop for processor chips

Aspects of the invention include receiving a first dictionary that includes key/value pairs for a first code listing. Key instances of the first dictionary include instruction addresses of the first code listing, and value instances of the first dictionary include hashes of data that uniquely identify instructions at the instruction addresses in the first code listing. A second dictionary that includes key/value pairs for a second code listing is received. Key instances of the second dictionary include hashes of data that uniquely identify instructions at instruction addresses in the second code listing, and value instances of the second dictionary include instruction addresses of the second code listing. A match between a value instance of the first dictionary and a key instance of the second dictionary is identified. Responsive to identifying the match, an instruction address is translated between the first code listing and the second code listing.

Unique instruction identifier that identifies common instructions across different code releases

Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Built-in testing of unused element on chip

The present invention provides an improved method for updating the settings of a processor or a processor core, respectively, concurrently to the operation of the respective processor system in which the processor or processor core, respectively, is running. This enables the insertion of new scan chain data and thus enabling the modification of the hardware characteristics of the processor.

Updating settings of a processor core concurrently to the operation of a multi core processor system

Reassignment of a physical processor backing a logical processor is performed concurrently to the operation of the processor. The operating state of one physical processor is loaded on another physical processor, such that the logical processor is backed by a different physical processor. This reassignment is performed concurrent to processor operation and transparent to the operating system.

Concurrent physical processor reassignment

Concurrent physical processor reassignment method

Special millicode instructions accelerate the 'inner loop' portion of a millicode routine to execute ESA/390 string instructions. Specifically, these millicode instructions are: Replicate Byte, Find Byte Equal, Find Byte Not Equal, Compare String Bytes instructions.

Specialized millicode instruction for string operations

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Stone Ridge, NY, United States of America

Christopher Raymond Conklin