Lsi Logic Corporation

Unisys Corporation

Motorola Corporation

Other

Stanford Telecommunications, Inc.

Christopher R Keate

Nadav Ben-Efraim

Ravi Bhaskaran

Dariush Dabiri

Bruce H Williams

Sergio Aguirre

Glenn A Arbanas

Jeffrey Mac Thornock

Kedar Shirali

Gregory B Vatt

Daniel A Luthi

Ting-Yin Chen

Jeffery M Thornock

Brian L Stockdell

Franklin W Floyd

An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an analog-to-digital converter, a Hilbert transform filter, a sideband selection switch, a complex multiplier, a carrier recovery. loop, a matched filter, and a decimator. The analog-to-digital converter oversamples an intermediate frequency (IF) signal from the tuner, and the Hilbert transform filter generates a Hilbert transform of the digital IF signal. An analytic IF signal can be generated from the digital IF signal by multiplying the Hilbert transform of the digital IF signal by j(&equals;sqrt(&minus;1)), and adding the resulting imaginary-valued signal to the digital IF signal. The sideband selection switch can &ldquo;flip&rdquo; the analytic IF signal by inverting the imaginary-valued signal. The complex multiplier multiplies the analytic IF signal by a complex-value sinusoid to shift the analytic IF signal to baseband. The resulting analytic baseband signal is match filtered and decimated to form a baseband double sideband signal with one sample per symbol period. The carrier recovery loop operates on the imaginary part of the analytic baseband signal to generate the complex sinusoid that shifts the analytic IF signal to baseband.

Method and apparatus for pilot-aided carrier acquisition of vestigial sideband signal

Digital interference rejection of a signal is accomplished by first converting the signal to digital. Then a second signal is generated and mixed with the first signal. This combined signal is then filtered. The signal can then be scaled as needed, resulting in a finely tuned, interference free signal.

Method and apparatus for digital interference rejection

An improved satellite receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip includes a lowpass filter having a configurable cutoff frequency, and the tuner chip uses a frequency signal to provide accurate adjustment of the cutoff frequency. A clock signal having a clock frequency is converted into a control voltage which determines the cutoff frequency of the lowpass filter. Consequently, the cutoff frequency may be increased by increasing the clock frequency, or decreased by decreasing the clock frequency. This configuration provides for improved cutoff frequency control in the presence of signal interference.

Method for lowpass filter calibration in a satellite receiver

An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator. The demodulator/decoder chip has a programmable counter configured to count cycles of the tuning frequency to provide a frequency-divided signal to a phase detector. The phase detector compares the frequency-divided signal to a reference frequency, and is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency to have a frequency which is a multiple of the resonance frequency. The demodulator/decoder chip also has a decoder which receives the baseband signal and converts it to a decoded signal.

Frequency synthesis architecture in a satellite receiver

The problems outlined above are in large part solved by an improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The front end includes a frequency synthesizer with an externally configurable charge pump on the tuner chip. The charge pump is coupled to a tank circuit having an adjustable resonance frequency. The resonance frequency can be adjusted over an entire octave by controlling the reverse bias voltage on a pair of varactors. A charge pump with a configurable gain is used to provide a control voltage to the tank circuit to provide a constant phase locked loop response over the frequency range of the tank circuit. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip is coupled to receive a receive signal and convert it to a baseband signal. The tuner chip includes an externally configurable charge pump, a tuning oscillator, and a downconverter. The charge pump receives binary inputs indicating a desired gain and responsively amplifies a phase difference signal by the desired gain to provide a correction signal to a loop filter. The loop filter is coupled to adjust a resonance frequency control voltage in a tank circuit according to the correction signal The tuning oscillator oscillates at the resonance frequency of the tank circuit. The downconverter receives a tuning frequency signal provided by the tuning oscillator, and combines it with a receive signal to produce a product signal.

Satellite receiver tuner chip with frequency synthesizer having an

A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which preserves frequency offset error tracking through a channel change. The demodulator/decoder receives the baseband signal and produces a compensation signal for canceling the frequency offset error. This is done using an element which generates a value indicative of the frequency offset error. Since the frequency offset error is independent of the selected channel, freezing the value indicative of the frequency offset error during a channel change enables a much faster acquisition of timing. In this manner faster channel acquisition is obtained.

System and method for fast channel switching in a satellite receiver

A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip converts a receive signal to a baseband signal using a tuning frequency signal generated from a tank circuit. The design of a package for the tuner chip maximally spaces the pins associated with high frequency signals by placing them on opposite sides of the chip (in the case of two high frequency signal sources) or (in the case of three high frequency signal sources) in a triangle formation with widely spaced vertices wherein at least two of the pins are adjacent to corners of the package. For two or more high frequency signal sources, a good determination of pin locations can be determined according to the formula P.sub.i =C+i.multidot..left brkt-bot.N/M.right brkt-bot., i=1, . . . , M, where P.sub.i are the pin numbers, N is a total number of pins around the perimeter of the package, M is a total number of the high frequency signal sources, and C is an offset number. Where a high frequency signal source has more than one associated pin, one pin number is found from the above formula, and the associated pins are placed on adjacent pins.

High frequency signal processing chip having signal pins distributed to

The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.

Single-chip DBS receiver

An apparatus and method for suppressing intermodulation noise in a radio frequency power amplifier. Intermodulation noise suppression is achieved by use of an amplitude limiter connected to the signal source and a shaping filter connected between the amplitude limiter and the power amplifier. The shaping filter may be a band-stop notch filter which attenuates intermodulation noise in a selected radio band or a bandpass filter which attenuates all out-of-band intermodulation noise. The intermodulation noise suppression of this invention causes the signal entering the power amplifier to be characterized by (1) a low peak-to-average envelope distribution and (2) low spectral content in the radio frequency bands to be protected.

Method and apparatus for intermodulation noise suppression in RF power

An improved DBS receiver front end architecture having a voltage controlled oscillator for frequency synthesis. The voltage controlled oscillator includes a tank circuit having an adjustable resonance frequency which may be varied over an octave. A tuning oscillator drives the tank circuit and provides a signal having that resonance frequency to a range extender which provides a tuning frequency. When enabled, the range extender doubles the input frequency, and when disabled, simply passes the input frequency through. A feedback path provides a control voltage to the tank circuit to adjust the resonance frequency and thereby cause the tuning frequency to be a multiple of a reference frequency. The range extender extends the tuning frequency range over two octaves without a loss of frequency resolution. Broadly speaking, the present invention contemplates a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip has a frequency doubler which provides a tuning frequency signal having a frequency twice that of an input frequency signal when the doubler is enabled, and a tuning frequency signal having a frequency equal that of an input frequency signal when the doubler is disabled. The tuner chip also has a tuning oscillator which provides the input frequency, and a downconverter coupled to receive the tuning frequency signal. The downconverter further receives a receive signal and responsively provides a product signal which is then converted to a baseband signal. The demodulator/decoder chip is configured to control the input frequency to the doubler, and further configured to convert the baseband signal to a decoded signal.

Extended range voltage controlled oscillator for frequency synthesis in

A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.

Satellite receiver tuner chip having reduced digital noise interference

A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form. The demodulator/decoder also includes a complex multiplier which multiplies the over-sampled digital baseband signal by the compensation signal to produce an offset-error-canceled signal. The complex multiplier is followed by a decimation block which reduces the sample rate of the offset-error-canceled signal to two samples per symbol period. This embodiment has a substantially increased frequency offset tracking range, which allows for the use of relaxed tolerances in the tuner and/or LNB.

System and method for digital tracking and compensation of frequency

A concatenated three layer Viterbi, Reed-Solomon/Deinterleaver and Descrambler forward error correction decoder may be utilized in digital video and audio systems, and for direct broadcast satellite applications. The digital signal may be a compressed video and audio signal transmitted from a direct broadcast satellite. Acquisition for three layers of synchronization are required, but once all three layers are in-sync, down stream data synchronization monitoring will suffice so that upstream synchronization monitoring can be disabled thus improving system robustness to noise bursts and false synchronization on false sync bytes generated at the transmission encoder during non-changing data signal conditions.

Reduction of false locking code words in concatenated decoders

An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump. The tuning oscillator is coupled to a tank circuit having an adjustable resonance frequency, and the charge pump is coupled to the tank circuit to control the resonance frequency. The downconverter receives a tuning frequency provided by the tuning oscillator, receives a receive signal, and combines the tuning frequency signal with the receive signal to produce a product signal. The lowpass filter acts to convert the product signal into a baseband signal, which may then be provided as a differential output signal.

Growing community of inventors

Chandler, AZ, United States of America

Christopher R Keate