Motorola Corporation

Nxp Usa, Inc.

Freescale Semiconductor,inc.

Christopher Paul Dragon

Wayne R Burger

Zihao M Gao

David Joseph Monk

Robert H Reuss

Daniel J Lamey

Walter Sherrard Wright

David Cobb Burdeaux

David K Lovelace

Robert A Pryor

Julio C Costa

Hernan A Rueda

David Q Ngo

Gordon C Ma

Natalino Camilleri

A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

Lateral insulated-gate bipolar transistor and method therefor

A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the guard region. The floating field plates and guard region act in some embodiments to 'smooth' the electrical field distribution along the termination area.

Semiconductor device with floating field plates

An RF power transistor with a metal design () comprises a drain pad () and a plurality of metal drain fingers () extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (-----), each section of metal including of one or more branch (-------) of metal having a metal width maintained within a bamboo regime.

RF power transistor device with metal electromigration design and method thereof

A semiconductor device ( ) having a gate ( ), a source ( ), and a drain ( ) with a gate bus ( ) and first ground shield ( ) patterned from a first metal layer and a second ground shield ( ) patterned from a second metal layer. The first ground shield ( ) and the second ground shield ( ) lower the capacitance of device ( ) making it suitable for high frequency applications and housing in a plastic package.

High frequency semiconductor device and method of manufacture

A semiconductor component includes a substrate (101), an electrode (105) located over the substrate (101), a heavily doped region (542) located in the substrate (101) and self-aligned to the electrode (105), an other heavily doped region (543) located in the substrate (101), a lightly doped region (422) located in the substrate (101) between the heavily doped regions (542, 543) and self-aligned to the electrode (105), and another lightly doped region (432) located in the substrate (101) between the lightly doped region (422) and the other heavily doped region (543).

Semiconductor component and method of manufacture

A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

Monolithic high frequency integrated circuit structure having a grounded

A junction isolated P-well is formed for high performance BiCMOS. Two dopants of opposite conductivity types are implanted and co-diffused inside an annular N-type region to form a narrow N-type buried layer positioned between two P-type regions. N-type buried layer is formed having P-type doped regions above and below the N-type buried layer so that the N-type buried layer is narrow. The P-type region above the N-type buried layer provides for a retrograde profile of the P-well formed above it. Besides the P-well isolation, the P-type region below the N-type buried layer acts as a ground plane which collects noise, which helps to prevent it from being coupled to other devices of the BiCMOS circuit.

Growing community of inventors

Tempe, AZ, United States of America

Christopher Paul Dragon