Broadcom Corporation

Other

Qualcomm Incorporated

Christopher Pasqualino

Stephen Petilli

Jeffrey S Bauch

David Vetea Greig

Richard Berard

Po Ngan Zee

Xuemin Chen

John S Walley

Erlend Olson

Shawn Val Johnson

Seong-Ho Lee

Ike Ikizyan

Hao O Phung

Sakyun Hwang

Rick Berard

Provided are systems and methods for providing enhanced motion detection. One system providing enhanced motion detection includes a smart display, an interface subsystem including a human interface device (HID), and a console having a processor configured to form communication links with the smart display and the interface subsystem and to provide motion detection feedback, using the smart display, to a user of the HID, where the HID is configured to sense motion of the HID and utilize a predictive model to characterize the motion of the HID. One interface subsystem includes a camera to sense motion of a user of the HID. One processor is configured to negotiate a reduced response latency with the smart display.

Systems and methods for providing enhanced motion detection

One embodiment of the present invention uses an abbreviated blanking period, in comparison to the standard VESA and CEA-EIA blanking periods, in order to send data, including low bandwidth, non-timing information, over one or more channels of the digital video link. By shortening the blanking period, the amount of time available for sending data in each scan line is increased, enabling the system to send more data over each channel. The inactive video portion of a scan line sent during vertical sync may also be used to send additional digital data. Shortening the blanking periods and/or using the inactive video sections of the horizontal scan lines adds to the overall data capacity of the link and may be used to send other digital data, such as multichannel audio, video, control, timing, closed captioning or other digital data.

Digital visual interface with audio and auxiliary data

The present invention relates to a system and method for transmitting auxiliary data in video encoding. The system and method receives first and second data, encoding the first data based on a state of at least one bit of the second data. The encoded first data and the second data is packaged into a single word and communicated.

Video encoding scheme supporting the transport of audio and auxiliary information

Encoding and decoding of video and non-video information may include creating a second symbol from a first codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the second symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the first codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the second symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The second symbol and the first codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the second symbol may be an 8-bit pre-TMDS symbol.

Method and system for generating high definition multimedia interface (HDMI) codewords using a TMDS encoder/decoder

Systems and methods for processing information are disclosed. The method may include creating a first symbol from a codeword. One or more of a TERC4 symbol, a TMDS symbol and/or a guard band symbol may be generated from at least a portion of the first symbol, if the one or more of the TERC4 symbol, the TMDS symbol and/or the guard band symbol is at least a portion of a signal to be transmitted. At least a portion of the codeword may be TMDS encoded to generate a TMDS symbol for the at least a portion of the signal to be transmitted. At least a portion of the first symbol may be TMDS encoded to generate a TERC4 symbol for the at least a portion of the signal to be transmitted and/or to generate a guard band symbol for the at least a portion of the signal to be transmitted.

A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered, synchronized, decoded, and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes an incorrect blanking period indication.

Synchronization of data links in a multiple link receiver

Encoding and decoding of video and non-video information may include creating a first symbol from a codeword. TERC4, TMDS and/or a guard band symbols may be generated from a portion or all of the first symbol during transmission. The TMDS symbol and/or the guard band symbol may be encoded so that they may be combined within a single symbol. At least a portion of the codeword may be TMDS encoded to generate a TMDS symbol for transmission. TMDS encoding of at least a portion of the first symbol may also generate a TERC4 symbol and/or a guard band symbol for the transmitted signal. The first symbol and the codeword may be generated from a portion or all of a received signal. The first codeword may be a 4-bit pre-TERC4 codeword, while the first symbol may be an 8-bit pre-TMDS symbol.

One embodiment of the present invention uses an abbreviated blanking period, in comparison to the standard VESA and CEA-EIA blanking periods, in order to send data, including low bandwidth, non-timing information, over one or more channels of the digital video link. By shortening the blanking period, the amount of time available for sending data in each scan line is increased, enabling the system to send more data over each channel. The inactive video portion of a scan line sent during vertical sync may also be used to send additional digital data. Shortening the blanking periods and/or using the inactive video sections of the horizontal scan lines adds to the overall data capacity of the link and may be used to send other digital data, such as multi-channel audio, video, control, timing, closed captioning or other digital data.

Digital visual interface with audio and auxiliary data cross reference to related applications

A dual link receiver terminates, recovers, channel aligns, and link aligns a plurality of primary link channels and a plurality of secondary link channels. The plurality of primary link channels and the plurality of secondary link channels are each received, bit recovered. synchronized, decoded and channel aligned. Then, the plurality of primary link channels and secondary link channels are link aligned. Link alignment operations first determine a relative misalignment between the plurality of primary link channels and the plurality of secondary link channels. A primary link delay is then applied to the primary link channels and a secondary link delay is then applied to the secondary link channels. A difference between the primary link delay and the secondary link delay is based upon the misalignment between the plurality of primary link channels and the plurality of secondary link channels. An enabling circuit precludes an incorrect blanking period indication.

A dual link transmitter constructed according to the present invention employs a single Phase Locked Loop (PLL) to service both a primary link and a secondary link during dual link mode operations. The structure of the dual link transmitter includes both a primary link PLL and a secondary link PLL. The primary link PLL produces a primary link clock and the secondary link PLL produces a secondary link clock. During dual single link operations, the primary link clock is used to service the primary link while the secondary link clock is used to service the secondary link. However, during dual link operations, the primary link clock is used to service both the primary link and the secondary link.

Dual link DVI transmitter serviced by single phase locked loop

The present invention relates to a system and method for generating a blanking period indicator signal from sync information in video timing. The invention comprises an auto polarity detect processor adapted to automatically detect the polarity of at least one sync signal and a generation processor adapted to generate a DE signal.

Automatic detection of sync polarity in video timing and generation of blanking period indicator from sync information

Dual link DVI transmitter serviced by single Phase Locked Loop

A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

Single ended termination of clock for dual link DVI receiver

A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.

System and method for recovering and deserializing a high data rate bit stream

The present invention comprises an apparatus and corresponding method for performing a built-in self-test (BIST) of a data communications system. The apparatus of the invention includes a transmitter, a receiver coupled to the transmitter and a test control system coupled to the transmitter and receiver for measuring a data error rate of the data communications system. The transmitter, receiver and test control system are disposed on a common substrate, such as an integrated circuit.

Growing community of inventors

Glendora, CA, United States of America

Christopher Pasqualino