Cirrus Logic Inc.

Other

Storage Technology Corporation

Christopher P Zook

Neal Glover

Richard T Behrens

William G Bliss

David E Reed

Trent O Dudley

Stephen Alan Turk

David R Welland

Paul M Romano

Alan J Armstrong

William L Witt

Tyson Tuttle

Diwakar Vishakhadatta

Jerrel P Hein

Marvin L Vis

John J Schadegg

John J Schadegg, Jr

Siamack Nemazie

Richard A Gill

Son H Ho

Keisuke Kato

Tony J Yoon

Ronald M Yamada

Sunil Bhaskar Chaudhari

Frederick Siu-Huang Au

A rate &#xbd;, d=1 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a d=1 Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=1 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. The channel encoding scheme increases the data density of the storage system due to the d=1 constraint and use of the Viterbi sequence detector. Further, the implementation advantageously uses the Viterbi sequence detector already provided in a read channel for detecting user data, and the cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.

Servo track address channel code for d=1 magnetic recording

Using a Berlekamp-Massey process operating with unique recursion rules, a fast correction subsystem performs, for each t-byte codeword having m-bit symbols, a series of error locator iterations, followed by a series of error evaluator iterations, followed by a series of correction iterations to generate and use an error pattern for correcting a codeword. The fast correction subsystem includes three sets of registers and various multipliers distributed over t&plus;1 component slices. In accordance with the recursion rules and multiplier implementations, only three types of registers ( ) are required per slice and all operations are preferably performed in m/2 or less clocks. A first set of registers (&ldquo;&sgr; registers&rdquo;) ultimately contains quantities which include coefficients of an error locator polynomial for the codeword. A second set of registers (&ldquo;&tgr; registers&rdquo;) are utilized, e.g., to update the &sgr; registers A third set of registers (&ldquo;R registers&rdquo;) ultimately contains quantities which include coefficients of an error evaluator polynomial for the codeword.

Error correction method and apparatus

A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for canceling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.

Sampled amplitude read channel employing pipelined reads to reduce the gap between sectors

A cost-effective high-throughput enumerative encoder is disclosed for encoding m-bit input datawords in an input data stream into n-bit output codewords in an encoded output data stream for use in a communication channel. The enumerative encoder comprises an input buffer for storing a plurality of bits in the input data stream, and a plurality of segmented compare tables for encoding the bits stored in the input buffer into the encoded output data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis. A cost-effective high-throughput enumerative decoder is also disclosed for decoding n-bit input codewords in a received data stream into m-bit output datawords in a decoded data stream for use in a communication channel. The enumerative decoder comprises an input buffer for storing a plurality of bits in the received data stream, and a plurality of segmented compare tables for decoding the bits stored in the input buffer into the decoded data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis.

Cost-effective high-throughput enumerative ENDEC employing a plurality of segmented compare tables

A sampled amplitude read channel is disclosed for reading a data sector recorded on a disk storage medium by detecting an estimated data sequence from a sequence of read signal sample values generated by sampling an analog read signal emanating from a read head positioned over the disk storage medium, the data sector comprising a user data segment and an embedded field comprising a known data segment. A sampling device samples the analog read signal to generate the read signal sample values and a trellis sequence detector detects a preliminary sequence from the read signal sample values. A post processor detects and corrects errors in the preliminary sequence using a syndrome generator responsive to the preliminary sequence representing the user data segment. The syndrome generator generates an error syndrome according to a predetermined error detection code. A boundary error compensator compensates for a boundary error event spanning the user data segment and the known data segment. A guided error corrector, responsive to the error syndrome, corrects errors detected in the preliminary sequence.

Sampled amplitude read channel employing a post processor with a boundary error compensator which compensates for boundary error events in a split-field data sector

In a disk storage system for digital computers (e.g., optical or magnetic disk drives) a sampled amplitude read channel is disclosed comprising a convolutional code channel encoder for encoding check bits into channel data recorded to a disk storage medium, a trellis sequence detector for detecting a preliminary sequence from read signal sample values generated during read back, a convolutional code syndrome generator for generating an error syndrome from the preliminary sequence, and a post processor for evaluating the error syndrome to detect and correct errors made by the trellis sequence detector. The post processor remodulates the preliminary sequence output by the trellis sequence detector into a sequence of estimated sample values which are subtracted from the actual read signal sample values to form a sequence of sample errors. When the error syndrome indicates the presence of an error in the preliminary sequence, the post processor processes the sample errors to determine the most likely location of the error and corrects it. The convolution code provides a significant performance gain due to its high rate and capacity to detect several of the dominant error events associated with the trellis sequence detector.

Error detection convolution code and post processor for correcting dominant error events of a trellis sequence detector in a sampled amplitude read channel for disk storage systems

A rotating storage medium has an index mark-indicating sequence recorded thereon, the index mark-indicating sequence comprised of bits distributed over plural servo wedges. The index mark-indicating sequence is comprised of at least one bit in each of a specified number of plural servo wedges per track, the specified number forming a subset of the servo wedges of the rotating storage medium. The specified number (subset) of plural servo wedges per track preferably is comprised of the servo wedge which contains the index mark a predetermined number (m&minus;1) of consecutive servo wedges. The subset of plural servo wedges may be positioned to precede and include the servo wedge which physically contains the index mark, or may be offset therefrom. Both the synchronization marks of the plural servo wedges and the index mark-indicating sequence are preferably fault tolerant. The bits used to form the sequence (which is checked against a predefined reference index mark-indicating sequence) are preferably recorded in synchronization marks of the specified number of plural servo wedges per track, and particularly in a sequence entry bit thereof.

Locating index mark in rotating magnetic storage media

A sampled amplitude read channel is disclosed for writing data to and reading data from a disk storage medium. A first channel encoder encodes a first j-k bits of a j-bit data block to generate first encoded data, and an ECC encoder encodes the first encoded data and a remaining k-bits of the data block to generate ECC redundancy symbols comprising a plurality of bits. A second channel encoder encodes the remaining k-bits of the data block and the ECC redundancy symbols to generate second encoded data. The first encoded data and the second encoded data are then output as channel data written to the disk storage medium.

Multiple-rate channel ENDEC in a commuted read/write channel for disk storage systems

An error correction code (ECC) processor which minimizes the probability of miscorrecting an ECC codeword in a multi-dimensional code, such as a product code, thereby avoiding the added latency in recovering from the miscorrection. Initially, the ECC processor sets the error correction power of the code to a minimum value so that the probability of making a miscorrection is low even though the probability of detecting an uncorrectable codeword is high. The ECC processor then performs iterative error correction passes over the multi-dimensional code and incrementally increases the error correction power if no corrections are made during a current pass. Increasing the correction power may render a previously uncorrectable codeword correctable, and after correcting the codeword, it may render a corresponding intersecting codeword in the other dimension correctable. If a codeword is corrected during a current pass, the correction power is reset to the minimum value for the next pass and the correction process continues. In this manner, the probability of making a miscorrection is minimized since the number of remnant redundancy symbols used to check for a miscorrection is maximized.

Error correction code processor employing adjustable correction power for miscorrection minimization

An encoder/decoder (ENDEC) avoids undesired sequences in encoded data blocks, such as quasi-catastrophic sequences, by essentially skipping over inputs that create the undesired sequences. Upon recognizing that a particular incoming data block has a value corresponding to an undesired sequence, the ENDEC does not use the problematic value for the incoming data block, but rather adds an offset to the value for the incoming data block, and uses the offset value for producing an encoded output sequence for the data block.

Selectively removing sequences from an enumerative modulation code

A sampled amplitude read channel is disclosed for disk storage systems (e.g., magnetic or optical) comprising a sampling device for sampling the analog read signal emanating from the read head positioned over a disk storage medium, a channel equalizer for equalizing the signal samples according to a desired partial response, a trellis sequence detector for detecting a preliminary sequence from the equalized signal samples, and a post processor for correcting errors in the preliminary sequence, including errors caused by the channel equalizers correlating the noise in the read signal. The preliminary sequence detected by the sequence detector is remodulated into ideal partial response samples and then subtracted from the actual signal samples to generate a sequence of sample errors. The sample errors are then filtered by a sample error filter, and the filtered sample errors are correlated with error event sequences corresponding to the most likely error events of the trellis sequence detector. The sample error filter compensates for the noise correlating effect of the channel equalizers by effectively whitening the noise to provide a closer approximation to an optimum maximum likelihood detector. When an error event is detected, the preliminary sequence is corrected with a correction sequence corresponding to the detected error event.

Sampled amplitude read channel employing noise whitening in a remod/demod sequence detector

A magnetic disk storage device employing an on-the-fly, multiple burst error correction system for detecting and correcting errors in data sectors stored on a magnetic disk, wherein each data sector comprises a data field and multiple sync marks for synchronizing to the data field. Multiple sync marks improve the probability of successful byte synchronization to the data field in the presence of noise in the system, such as defects in the storage medium. Further, a sync mark may be embedded within the data field to facilitate byte resynchronization when synchronization is lost.

A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a sampling device, such as an analog-to-digital converter (A/D), for sampling the analog read signal to generate the discrete time sample values and for sampling at least one other auxillary analog input signal, such as a servo control signal. In this manner, performance characteristics of the read channel can be measured, such as the driving current applied to the servo control voice coil motor (VCM), without requiring additional hardware.

Sampled amplitude read channel for reading user data and embedded servo

A multi-layered error detection and correction (EDAC) system is disclosed for processing an error correction code (ECC) typically employed in optical disk storage devices. A first layer of the EDAC system includes a primary ECC, such as a multiple burst Reed-Solomon code, and a second layer incudes a secondary ECC, such as a CRC code, for use in verifying the validity of the corrections made using the primary ECC. The primary ECC is multi-dimensional and, in the embodiment disclosed herein, it is a two-dimensional P/Q product code typically employed in a CD-ROM storage device. The secondary ECC operates in unison with the primary ECC. As the EDAC system processes and corrects the data using the primary ECC, the EDAC system also simultaneously updates the secondary ECC. In this manner, when the EDAC system is finished processing the data using the primary ECC, the validation syndrome generated by the secondary ECC is available immediately for checking the validity of the corrections. Consequently, the additional pass otherwise required when no uncorrectable errors are encountered after completing a P or Q pass is obviated. To significantly increase the processing of the EDAC system, error-free code words are skipped during the iterative passes of the multi-dimensional primary ECC. When a code word is skipped, the validation syndrome generated using the secondary ECC is adjusted to account for the skipped data bytes.

Error correction and concurrent verification of a product code

An error correction processor is disclosed for correcting errors in binary data read from a disk storage medium, wherein the binary data comprises a first and second set of intersecting ECC codewords of a multi-dimensional codeword. The error correction processor comprises a data buffer for storing the ECC codewords read from the disk storage medium; a syndrome generator for generating ECC syndromes in response to a codeword in the second set; an error-locator polynomial generator for generating an error locator polynomial .sigma.(x) in response to the ECC syndromes; a selector for selecting between the error-locator polynomial .sigma.(x) and an erasure polynomial .sigma.(x).sub.EP, wherein:

Growing community of inventors

Longmont, CO, United States of America

Christopher P Zook