Apple Inc.

Christopher P Tann

Sandro Hermann Pintz

Marc Albrecht

Paolo Sacchetto

Arthur L Spence

Peter F Holland

Taesung Kim

Guy Cote

David S Zalatimo

Chaohao Wang

Mahesh B Chappalli

Fenghua Zheng

Brijesh Tripathi

David W Lum

Jerrold Von Hauck

Ian C Hendry

Guy Côté

Jason N Gomez

Vanessa Cristina Heppolette

Ross Thompson

Malcolm D Gray

Prasanna Nambi

Paul Stephen Drzaic

Jean-Pierre Simon Guillou

Zhibing Ge

Joshua P De Cesare

Yifan Zhang

Tae-Wook Koh

Satish S Iyengar

Jun Qi

Jim Chen Chou

Hyunwoo Nho

James E C Brown

Ilie Garbacea

Yue Jack Chu

Stephan Lachowsky

Wei Hsin Yao

Keith Alan Cox

Yafei Bi

Kingsuk Brahma

Martin Paul Grunthaner

Jie Won Ryu

Brad W Simeral

Ali Sazegari

Weijun Yao

Marc Joseph DeVincentis

Shih-Chyuan Fan Jiang

Ruchi Wadhawan

Yi Huang

Lu Zhang

Koorosh Aflatooni

Mohammad Ali Jangda

Rohit Kumar Gupta

Chun Lu

Jiayi Jin

Manu Agarwal

Howard H Tang

Myung-Je Cho

Ramana V Rachakonda

Rohit Natarajan

Shereef Shehata

Lars M Lindberg

Haifeng Li

Jun Jiang

Alexey Kornienko

Hari Ganesh R Thirunageswaram

Robert L Ridenour

Ardra Singh

Lei Zhao

Ruo-Gu Huang

Daniel J Drusch

Shawn P Hurley

Kristan Jon Monsen

Jongyup Lim

Zhe Hua

Alan M Dunn

Adam J Machalek

To reduce overall power consumption for an electronic display power management integrated circuit (PMIC), one of multiple electric power converters and/or electric power regulators may be selected based on an electrical load (e.g., due to the total brightness of the content displayed) on the electronic display at a given moment. In some embodiments, the PMIC may include a less efficient heavy load converter designed with high-current handling capability and a more efficient light load (e.g., low current) converter with lower current handling capability. A controller may dynamically select between the converters depending on a present load or an expected load on the electronic display.

Content-aware dynamic power converter switching for power optimization

A device may include an electronic display to display an image frame based on first and second color component input image data. The electronic display may include a first illuminator to generate a first light at a first brightness level, a second illuminator to generate a second light of a different color at a second brightness level, a first set of pixel locations to emit the first light based on a first set of pixel values, and a second set of pixel locations to emit the second light based on a second set of pixel values. The electronic device may also include pixel contrast control circuitry that determines the first brightness level and the first set of pixel values based on the first color component input image data and determines the second brightness level and the second set of pixel values based on the second color component input image data.

RGB pixel contrast control systems and methods

An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

Always-on display signal generator

An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

Guaranteed real-time cache carveout for displayed image processing systems and methods

An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.

Burn-in statistics and burn-in compensation

Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

Timestamp based display update mechanism

The configuration buffer may be divided into partitions that may effectively function as multiple linked configuration buffers. The linked partitions may each be associated with a portion of the display pipeline (e.g., an image process block) and may each be responsible for loading configuration entries into the programmable register(s) of a portion of the display pipeline. In this manner, the partitions may load the associated programmable register(s) of the display pipeline substantially simultaneously, reducing the time used to configure the entire display pipeline. Since configuration of the display pipeline may occur during the blanking period, a reduction in display pipeline configuration time may reduce the blanking period and increase the time for driving pixels of the display, thereby improving perceived image quality (e.g., pixel yield of the display panel).

Electronic display reduced blanking duration systems and methods

In situations with reduced image changes, display panels, such as the ones disclosed herein, may reduce their power consumption by performing self-refresh cycles, in which they may display locally stored data in the display panel instead of retrieving it from an image buffer. Methods and circuitry for management of the self-refresh cycle may reduce jitter, luminance errors, and/or flickers that may be caused by untimely self-refresh cycles that may occur as a result of latency in the image buffer. In some implementations, the display panel may have a dedicated low latency input that notifies an arrival of an incoming image. In some implementations, the self-refresh cycles of the panel may be managed by a host or a buffer that is responsible for sending the images.

Collision avoidance schemes for displays

System and method for improving displayed image quality of an electronic display that displays a first image frame by applying a first voltage to a display pixel and a second image frame directly before the first image frame by applying a second voltage to the display pixel. A display pipeline is communicatively coupled to the electronic display and receives first image data corresponding with the first image frame, where the image data includes a first grayscale value corresponding with the display pixel. Additionally the display pipeline determines an inversion balancing grayscale offset based at least in part on the first grayscale value when polarity of the first voltage and polarity of the second voltage are the same and determines magnitude of the first voltage by applying the inversion balancing grayscale offset to the first grayscale value to reduce likelihood of a perceivable luminance spike when displaying the first image frame.

Inversion balancing compensation

A data processing system can store a long-term history of pixel luminance values in a secure memory and use those values to create burn-in compensation values that are used to mitigate burn-in effect on a display. The long-term history can be updated over time with new, accumulated pixel luminance values.

Long-term history of display intensities

An electronic device may include a display panel to display an image and a display pipeline to process image data for the image. The display pipeline may include a controller to determine a first potential presentation time based on a maximum refresh rate of the display panel. The controller may also determine if a second target presentation time of a second image is equal to the first potential presentation time before a pipeline configuration time, and if the second target presentation time of the second image is equal to a second potential presentation time that occurs after the first potential presentation time and before a first pre-notification time occurring before the pipeline configuration time. The controller may output a first pre-notification signal at the first pre-notification time that instructs the display panel to pause self-refreshes until after the second image is displayed.

Electronic display frame pre-notification systems and methods

Devices and methods for useful in providing localized synchronized and/or dynamic in-band internal gamma code adjustment per frame period are provided. By way of example, a display panel includes a data driver, which includes a first DAC configured to provide an internal gamma voltage signal to cause a first adjustment to an image data signal. The first adjustment is configured to selectively adjust the image data signal based at least in part on a refresh rate or a frame rate of the display panel. The data driver includes a second DAC coupled to the first DAC and configured to provide an external gamma voltage signal configured to provide a second adjustment to the image data signal, and an output buffer configured to supply the image data signal to pixels of the display panel, wherein the image data signal comprises the first adjustment and the second adjustment.

Internal gamma correction for electronic displays

The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below.

Low power display device with variable refresh rates

Growing community of inventors

San Jose, CA, United States of America

Christopher P Tann