Intel Corporation

Sony Group Corporation

Christopher P Mozak

Theodore Zale Schoenborn

James A McCall

Kuljit Singh Bains

Christopher E Cox

Zvika Greenfield

Bryan L Spry

John B Halbert

John V Lovelace

James M Shehadi

Kevin B Moore

Christopher E Yunker

Mahmoud Elassal

Bryan K Casper

Aaron K Martin

Tomer Levy

Hsien-Pao Yang

David G Ellis

Alexey Kostinsky

Randy B Osborne

Bill Nale

Tonia G Morris

Nagi Aboulenein

Zale Theodore Schoenborn

Victor Zia

Roger K Cheng

Rebecca Z Loop

Michael Gutzmann

Robert J Friar

Alvin Shing Chye Goh

Pavan Kumar Kappagantula

Steven T Taylor

Yan Fu

Ralph S Li

Chin Wah Lim

Anant Balakrishnan

Isaac Ali

Paul S Cheses

Danny Naiger

Akshith Vasanth

Mohammed G Mostofa

James E Jaussi

Nasser A Kurd

Inder M Sodhi

Robert J Royer, Jr

Ganapati Srinivasa

Eng Hun Ooi

Bruce Querbach

Maynard C Falconer

Shaun M Conrad

Praveen Mosalikanti

Mozhgan Mansuri

Stanley Steve Kulick

Jeffrey D Gilbert

Philip R Lehwalder

Ritesh B Trivedi

Xiuting C Man

Jay Joseph Nejedlo

Harishankar Sridharan

Navindra Navaratnam

Raymond Chong

Brian R Mcfarlane

Philip Abraham

Adam J Norman

Pavel Konev

Hong Yun Tan

Hariprasath Venkatram

Bee Min Teng

Jayasekhar Tholiyil

Alex Thomas

Chris Yunker

Ee Loon Teoh

Rony Ghattas

Eliyah W Kilada

Rajesh Inti

Senthil Kumar Sampath

Noam Lupovich

Kushal Sreedhar

Gabriel J Thompson

Jeffery L Krieger

Olga Fomenko

Charles D Lucas

Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.

Techniques for duty cycle correction

In a memory subsystem, a memory controller can put its physical interface (PHY) into a low power state when an associated memory device is in self-refresh. Instead of powering on the interface and then triggering the memory device to exit self-refresh, or instead waiting for the physical interface to be powered up prior to waking the memory device from self-refresh, the memory controller can instruct the PHY to send a self-refresh exit command to the memory device and power up the physical interface in parallel with the memory device coming out of self-refresh. The memory controller can power down a high speed clock path of the PHY and use a slower clock path to send the self-refresh exit command before powering the high speed clock path back up.

Fast self-refresh exit power state

A scheme intelligently balances existing TM0 resources to simultaneously boost both AC and DC power delivery topologies without incurring a penalty on either area or IR drop. TM0 tracks are either regular or staples. Regular tracks are continuous across the width of an active silicon. Staples are located right under the respective TM1 (Top Metal 1) tracks. TM1 is above TM0 in the hierarchy of metal layers. The staples aid in increasing the total TV0 (Top Via 0 that connects TM0 to TM1) density for all supplies simultaneously as they are consecutively track-shared between the TM1 tracks. This boost in via density helps reduce the net series resistance of the MIM capacitor as the Manhattan (displacement) distance between the supply and ground vias is now reduced. The outcome is a high-density high-bandwidth MIM capacitor, located between the main power distribution layers in the die metal stack—TM0 and TM1.

Apparatus and method to increase effective capacitance with layout staples

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Techniques for command bus training to a memory device

An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.

Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus

A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Applying chip select for memory device identification and power management control

An apparatus is provided which comprises: a power gate device coupled to a gated power supply node and an ungated power supply node; and a control circuitry coupled to the power gate device, wherein the control circuitry is to turn on the power gate device by providing at least two bias voltages separated in time to gradually turn on the power gate device.

Power gate ramp-up control apparatus and method

A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

DDR memory bus with a reduced data strobe signal preamble timespan

A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Efficiently training memory device chip select control

Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.

Strong arm latch with wide common mode range

An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Dual power I/O transmitter

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Beaverton, OR, United States of America

Christopher P Mozak