International Business Machines Corporation

Qimonda North America Corporation

Infineon Technologies Ag

Globalfoundries Inc.

Macronix International Co., Ltd.

Infineon Technologies North America Corp.

Qimonda North American Corp.

Christopher P Miller

Claude Louis Bertin

Russell J Houghton

John Atkinson Fifield

William R Tonti

Kenneth E Beilstein, Jr

David J Perlman

Wayne John Howell

Gordon A Kelley, Jr

Hsiang-Lan Lung

Paul A Farrar

Edmund Juris Sprogis

Howard L Kalter

Matthew Joseph BrightSky

Nanbo Gong

Bruce G Hazelzet

Wei-Chih Chien

Dale E Pontius

Steven William Tomashot

Michael A Killian

Gustav Schrottke

Donald W Labrecque

Gordon Arthur Kelley

Jody John VanHorn

Christopher W Scoville

Dennis Charles Dubois

Steffen A Loeffler

Timothy Jay Dell

Clarence Rosser Ogilvie

Albert Manhee Chu

Mark William Kellogg

Robert E Busch

Wolfgang Hokenmaier

Jeffrey Scott Zimmerman

Jean-Marc Dortu

Paul C Stabler

Jim L Rogers

Willem B Van Der Hoeven

Andre Sturm

Mark Beiley

Steven W Thomashot

Steven Platt

Charles S Patton

Jochen Hoffman

Charles Drake

A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.

Multi-level cell threshold voltage operation of one-selector-one-resistor structure included in a crossbar array

A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

Voltage charge pump with segmented boost capacitors

Various embodiments include an integrated circuit (IC) structure having: a chip control logic; a chip power system connected with the chip control logic; and a voltage island connected with the chip control logic and the chip power system, the voltage island including: an interface component for interfacing with the chip power system and the chip control logic; a logic island connected with the interface component; and a voltage island power system connected with the interface component and the logic island, the voltage island power system independently controlling a voltage supplied to the logic island.

Integrated circuit having regulated voltage island power system

A load-sensing voltage charge pump system may include a plurality of reference voltage inputs including a target voltage input. The system may also include a plurality of voltage charge pump segments equal in number to the plurality of reference voltage inputs. A voltage charge pump segment may include: a regulator that receives a reference voltage, and a voltage charge pump that outputs a current to a load at a sensed voltage. The regulator may enable each of the voltage charge pump segments, when the sensed voltage is less than or equal to the one of the reference voltages and the target voltage. The system may include a boosted line connected in parallel to an output of each of the voltage charge pump segments. The boosted line may receive the current at the sensed voltage from each of the voltage charge pump segments that is enabled.

Load sensing voltage charge pump system

Methods and circuit arrangements are provided for improving equalization of sense nodes of a sense amplifier in a semiconductor memory device. When a memory array segment on a side a sense amplifier has a bitline leakage anomaly for which the sense amplifier is to be isolated when that memory is in an unselected state, isolation of the sense amplifier from the memory array segment is delayed when transitioning from a selected state of the memory array segment to an unselected state of the memory array segment. The duration of the delay is sufficient to allow time for equalization of the sense nodes of the sense amplifier before isolating the sense amplifier from the memory array segment.

Delayed sense amplifier multiplexer isolation

A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.

Reducing leakage current in memory device using bitline isolation

Growing community of inventors

Underhill, VT, United States of America

Christopher P Miller