Intel Corporation

Christopher P McAllister

Thomas D Fletcher

Thomas J Mozdzen

Timothy S Beatty

Orlando Davila

A boundary scan cell for testing an integrated circuit comprises an output buffer for driving a pad of the integrated circuit, a capture register coupled to the pad through the output buffer, and an input buffer drives a signal present at the pad to a node coupled to core logic of the IC. A first multiplexer is included to have a first input coupled to the node, a second input coupled to data of a previous scan stage, and an output coupled to the capture register. Logic circuitry selectively enables/disables the input and output buffers responsive to first and second control signals such that the I/O buffers can drive the pad and, at the same time, drive the input buffer, the output of which is coupled to the input of the capture register.

JTAG boundary scan cell with enhanced testability feature

An integrated circuit includes: a comparator coupled in a configuration to compare two voltages. One of the two voltages includes a semiconductor junction voltage drop. The other of the two voltages includes a voltage signal, X V.sub.t, where V.sub.t is a thermal voltage and X includes a selected signal value, which modulates the thermal voltage. The configuration includes a feedback path to vary X until X V.sub.t approximately equals the voltage including the semiconductor junction voltage drop.

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Chandler, AZ, United States of America

Christopher P McAllister