Motorola Corporation

Christopher P LaRosa

Michael J Carney

Christopher John Becker

Tracie Ann Schirtzinger

Brian David Storm

Fuyun Ling

James C Baker

David L Steckl

Dave Steckl

Tracie Schitzinger

An apparatus for acquiring a pseudo-random (PN) sequence timing for a code division multiple access (CDMA) radiotelephone. A buffer stores samples of representations of at least one pilot signal. A correlator coupled to the buffer is operable to correlate at least a portion of the samples with a PN sequence at each of a plurality of different PN offsets to produce corresponding correlation energies. A controller coupled to the correlator interrupts the correlator as soon as the PN sequence at a particular PN offset produces a correlation energy at least equal to an energy threshold.

Method and apparatus for acquisition of a spread-spectrum signal

A method () and a receiving unit () for demodulating a multi-path signal are described herein. The receiving unit () may be configured to receive the multi-path signal. The receiving unit () may include an input buffer controller (), an input buffer (), a rake finger (), and a sum generator (). The input buffer () may be configured to store data samples associated with a plurality of paths of the multi-path signal. The input buffer controller () may be configured to time-align the data samples relative to each other, and to delay the data samples. The rake finger () may be configured to de-spread and to accumulate the delayed data samples for a sub-correlation length. The sum generator () may be configured to combine a plurality of outputs from the rake finger (). Each of the plurality of outputs corresponds to one of the plurality of paths of the multi-path signal.

Method and receiving unit for demodulating a multi-path signal

A method of activating a radiotelephone operable in a spread-spectrum multiple access radiotelephone system. A searcher receiver () is activated, and the searcher receiver () acquires a PN sequence timing of a pilot signal. At least one demodulation branch () is activated after activation of the searcher receiver (), and the demodulation branch synchronizes to the PN sequence timing of the selected pilot signal after the searcher receiver () has acquired the PN sequence timing.

Method of and apparatus for activating a spread-spectrum radiotelephone

By time-sharing demodulator hardware between a primary data path (,), a power control data path (,), and a received signal strength indicator (RSSI) path (,), an entire power control data path (,) can be implemented in a demodulator (,) of a spread spectrum subscriber unit receiver with a low increase in gate count. The primary data path (,) and the power control data path (,) time-share a complex conjugate generator (,), a complex multiplier (,), and a real component extractor (,). Due to timing requirements, though, the channel estimation filter (,) of the primary data path cannot be time-shared with the power control data path. Instead, dynamic coefficient scaling is added to an infinite-duration impulse response (IIR) filter in the RSSI path (,) so that the IIR filter (,) with dynamic coefficient scaling can be time-shared between the RSSI path (,) and the power control data path (,).

Demodulator having an infinite-duration impulse response filter with dynamic coeffiecient scaling

By time-sharing demodulator hardware between a primary data path (165), a power control data path (161), and a received signal strength indicator (RSSI) path (163), an entire power control data path (161) can be implemented in a demodulator (140) of a spread spectrum subscriber unit receiver with a low increase in gate count. The primary data path (165) and the power control data path (161) time-share a complex conjugate generator (270), a complex multiplier (280), and a real component extractor (290). Due to timing requirements, though, the channel estimation filter (240) of the primary data path cannot be time-shared with the power control data path. Instead, dynamic coefficient scaling is added to an infinite-duration impulse response (IIR) filter in the RSSI path (163) so that the IIR filter (250) with dynamic coefficient scaling can be time-shared between the RSSI path (163) and the power control data path (161).

CDMA power control channel estimation using dynamic coefficient scaling

A digital filter (200) suitable for use in a CDMA or other burst-mode communication device (100) employs precombining of filter coefficients to reduce filter complexity and power dissipation. The digital filter (200) includes a coefficient storage circuit (216) for storing the precombined coefficients, a selection circuit (212) for selecting appropriate precombined coefficients in response to the input signal and a combining circuit (214) for combining the appropriate precombined coefficients to produce a filtered signal.

Efficient digital filter and method using coefficient precombing

In the digital FM demodulator (330), a hard limiter (333) receives a modulated analog IF signal and limits the voltage of the IF signal to two levels. Next, a direct phase digitizer (336) uses zero-crossings of the limited IF signal to generate N-bit digital words. A phase differential circuit (340) computes the phase shift of the signal from the direct phase digitizer over a predetermined time interval. The dynamic range of the phase differential signal can be increased by replacing the phase differential circuit (340) with a high-resolution phase differential circuit (700). After digital demodulation and filtering and gain control by audio processor (360), the recovered signal is forwarded to a speaker (390) to produce an audio output. Thus, the digital FM demodulator both avoids problems common to analog discriminator circuitry and offers a reduced complexity, size, and power consumption alternative to conventional digital FM demodulators.

Digital FM demodulator

A radio receiver directly digitizes the phase of an intermediate frequency (IF) signal with a desired resolution. The frequency of the reference oscillator in the direct phase digitizer is reduced when compared to the frequency previously required for the same resolution. The reduction in the reference oscillator frequency is accomplished by differentiating between IF zero-crossings that occur during the first half of a reference oscillator cycle and zero-crossings which occur during the second half of the reference oscillator cycle. The apparatus utilizes 2 zero-crossing detectors, the first zero-crossing detector is driven by a positive edge of the reference oscillator signal and the second zero-crossing detector is driven by a negative edge of the reference oscillator signal. Depending upon the alignment of the negative edge zero-crossing indicator and the positive edge zero-crossing indicator, the N-bit phase signal is modified or shifted by one-half a phase sector.

Direct phase digitizing apparatus and method

This patent application discusses a direct phase digitizing apparatus (303) for use in a radiotelephone (101). The direct phase digitizing apparatus (303) accepts a first analog signal (309) having a phase, a voltage range and a first frequency. First, the direct phase digitizer generates an estimated phase map (611) having a second frequency and N-bits of resolution. Second, the direct phase digitizer detects a predetermined-voltage crossing (409) of the first analog signal (309). Third, using the predetermined-voltage crossings, the direct phase digitizer samples the estimated phase map. Fourth, a digital phase signal (623) is generated using the samples of the estimated phase map.

Apparatus and method for direct phase digitizing

The present disclosure includes a discussion of a method of and apparatus for channel quality estimation (CQE) in a receiver. Each channel is divided into observation intervals and sub-intervals. The duration of the sub-interval is chosen as the largest interval in which the channel is essentially static. The CQE collects error information for each symbol of the sub-interval, forming a sub-interval error value. The CQE maps the sub-interval error value into a sub-interval bit error rate (BER) estimate. The mapping is a non-linear function dependent on the specific radio system. Then, the CQE averages the sub-interval BER estimates over the entire observation interval, forming an interval BER estimate. Finally, the CQE compares the interval BER estimate to a predetermined threshold, forming a channel quality estimation decision for each observation interval.

Method and apparatus of estimating channel quality in a receiver

A method of and apparatus for compensating a received signal's phase compensates for the distortion caused by the asymmetrical characteristics of a voltage limiter. This compensation allows the received signal to be sampled at the positive and negative zero-crossings reducing the requirements of a local oscillator in a radiotelephone system. First, the phase of the received signal is sampled at the positive and negative zero-crossings, forming a corresponding positive-crossing and a negative-crossing phase value for the received signal. Second, the negative-crossing and positive-crossing phase values are combined, forming a first difference signal. Third, an estimated error signal is formed using the first difference signal. Fourth, the estimated error signal is combined with the positive or negative zero-crossing phase signals, substantially eliminating the asymmetrical distortion.

Phase compensation method and apparatus

The present patent application discusses a frequency translation apparatus for altering the effective frequency of the phase information of an input signal (115). The input signal (115) has a first phase (.theta.(t)) and a first frequency (f.sub.i). The phase of the input signal is extracted and digitized at a second frequency (f.sub.o), forming a second N-bit digital phase signal (.theta.'(t))(311). The frequency translation apparatus generates a third digital phase signal (319) which approximates the difference between .theta.(t) and .theta.'(t). Then, the frequency translation apparatus combines the second digital phase signal and the third digital phase signal, forming a fourth digital phase signal (307) substantially approximating the first phase signal.

Frequency translation apparatus and method

The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.

Apparatus for and method of synchronizing a clock signal

The present disclosure includes a discussion of a decision-directed clock recovery system which includes circuitry to prevent false-locking and accelerate acquisition on a known symbol patterns. The clock recovery system has at least two control circuits. Each control circuit has an effective bandwidth and also generates a clock signal. The clock recovery system samples the received data signal using the two clock signals, forming a corresponding first and second sampled signal. The sampled signals are used to generate corresponding symbol decisions. The symbol decision signals are processed to detect a known symbol pattern in the received data signal. Upon detection of the known bit sequence, the characteristics of the clock recovery system are modified, namely, the effective bandwidth of the control circuits are modified.

Method and apparatus for modifying a decision-directed clock recovery

A clock recovery circuit employs a method of and apparatus for adjusting the phase of a recovered clock signal. The clock signal is recovered from a received input signal. The clock recovery circuit generates a sampling clock signal which is synchronous with the received signal. Additionally, the phase adjustment apparatus generates at least two error signals which indicate the quality of the received signal at different sampling phases. The smallest error signal is referred to as the minimum error value. Each error signal is compared to the minimum error value, creating a corresponding normalized error magnitude signal. Each normalized error magnitude signal is processed to determine the desired phase of the sampling clock signal. Dependent upon the processing of the normalized error magnitude signals, the phase of the sampling clock signal is either shifted or maintained until the next sampling point. The phase of the sampling clock signal is maintained during periods indicating poor received input signal quality.

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Lake Zurich, IL, United States of America

Christopher P LaRosa