Motorola Corporation

Christopher P La Rosa

Michael J Carney

Brian David Storm

Colin D Frank

Phillip D Rasky

Christopher John Becker

Michael A Eberhardt

A searcher receiver ( ) includes a sample buffer ( ) which stores signal samples loaded using a real time clock. A real time linear sequence generator (RT LSG) ( ) stores an initial state and is clocked using the real time clock. The contents of the RT LSG are loaded into a non-real time linear sequence generator (NRT LSG) ( ) when sample processing begins. Samples are correlated using a non-real time clock to allow signal processing to be uncoupled from the chip rate. The analog front end ( ) may be powered down or tuned to another frequency during non-real time processing.

Method and apparatus for acquiring a pilot signal in a CDMA receiver

A searcher receiver (,) includes a sample buffer (,) which stores signal samples loaded using a real time clock. A real time linear sequence generator (RT LSG) (,) stores an initial state and is clocked using the real time clock. The contents of the RT LSG are loaded into a non-real time linear sequence generator (NRT LSG) (,) when sample processing begins Samples are correlated using a non-real time clock to allow signal processing to be uncoupled from the chip rate. The analog front end (,) may be powered down or tuned to another frequency during non-real time processing.

A searcher receiver (114) includes a sample buffer (202) which stores signal samples loaded using a real time clock. A real time linear sequence generator (RT LSG) (206) stores an initial state and is clocked using the real time clock. The contents of the RT LSG are loaded into a non-real time linear sequence generator (NRT LSG) (208) when sample processing begins. Samples are correlated using a non-real time clock to allow signal processing to be uncoupled from the chip rate. The analog front end (108) may be powered down or tuned to another frequency during non-real time processing.

A RAKE receiver (112) includes a plurality of fingers (122, 124, 126, 128). Each finger includes a demodulator (402) for demodulating a ray of a multipath signal and a time tracking circuit (404) for controlling the time position of the finger in accordance with time position of the ray. A low delay-spread condition is detected and the positions of two adjacent fingers are controlled to prevent convergence of two or more fingers about a common time position. By maintaining finger timing separation, path diversity is exploited by the RAKE receiver even during the low delay-spread condition to improve receiver performance.

Rake receiver and finger management method for spread spectrum

A unique method and apparatus determines signal quality and/or bit reliability information for a plurality of phase modulated information symbols. This is accomplished by first detecting the phase of the received phase modulated signal (201). The resulting phase estimate is then compared against the nearest expected phase value to form a phase error signal (202). The phase error signal is then mapped into a symbol quality estimate (205/206), which is then averaged over multiple symbol intervals to form a signal quality indicator (207). Finally, bit reliability information is generated by weighting the in-phase (I) and quadrature (Q) components of the phase estimate by the derived signal quality indicator (209). With such a method and apparatus, signal quality and/or bit reliability information can be determined without the need for signal amplitude information.

Method and apparatus for determining signal quality

A demodulator (414) for improving bit error rate performance where alternating bit patterns produce the worst occurrences of bit errors. The demodulator (414) consists of a zero threshold comparator circuit (502), a first threshold detector circuit (508), and a second threshold detector circuit (504). The zero threshold comparator circuit (502) receives a frequency information signal and slices it into a plurality of bits (522). The first threshold detector circuit (508) compares the frequency information signal to a predetermined threshold, which is selected to optimize bit error rate performance. The second detector threshold circuit (504) is used to ensure that an alternating bit pattern has occurred. The demodulator (414) also includes a control device circuit (516) for coupling the plurality of bits (522) from the zero threshold comparator (502) to the output of the control device as a decision output signal (416) when the frequency information signal falls outside of either the first or second detector thresholds (508), (504). If the frequency information signal falls within both thresholds of the detector devices then the decision output signal (416) for the control device (516) is formed by inverting the bit decision from the previous bit interval.

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Lake Zurich, IL, United States of America

Christopher P La Rosa