Advanced Micro Devices Corporation

Vantis Corporation

Lattice Semiconductor Corporation

Christopher O Schmidt

Sunil D Mehta

Ali A Iranmanesh

Xiao-yu Li

Robert H Tu

Robert W Bower

Peter S Gwozdz

William L Price

Xiao Yu Li

An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.

EEPROM cell with self-aligned tunneling window

A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000&deg; C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Optimization of S/D annealing to minimize S/D shorts in memory array

A non-volatile memory cell structure includes a floating gate, a reverse breakdown hot carrier injection element and a sense transistor. The reverse breakdown hot carrier injection element is at least partially formed in a first region of a semiconductor substrate under at least a portion of the floating gate. The sense transistor is at least partially formed in a second region of a semiconductor substrate, isolated from the first region, and under at least a portion of the floating gate. A read transistor may be connected to the sense transistor. In one embodiment, the read transistor is at least partially formed in the second region of a semiconductor substrate, and connected to the sense transistor.

Floating gate memory cell structure with programming mechanism outside the read path

A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.

Boron doped silicon capacitor plate

A non-volatile memory cell structure which includes a floating gate, at least one injection element and a sense transistor. The injection element is at least partially formed in a first polysilicon layer. The floating gate is provided in a second polysilicon layer and capacitively coupled to the reverse breakdown element. The sense transistor is at least partially formed in a region of a semiconductor substrate, and connected to the floating gate. The structure may further comprise a control gate capacitively coupled to the floating gate and may be formed in said first polysilicon layer.

Avalanche programmed floating gate memory cell structure with program

An improved semiconductor device is presented, the improvement comprising a slot collector contact region (38). The slot collector contact region (38) is formed in a semiconductor substrate (39) adjacent to base and emitter regions (40,44) of the bipolar semiconductor device. The slot collector contact region (38) is comprised of a slot filled with a filler material. In a preferred embodiment of the invention, the slot collector contact region (38) is separated from the base and emitter regions (40,44) by an insulating layer (52).

Slot collector transistor

An improved integrated circuit structure is disclosed which comprises a substrate having one or more active device slots with active elements of an active device formed therein and an isolation slot surrounding the one or more active device slots with an inner wall contiguous with the outer wall of the one or more active device slots. The active elements in the one or more active device slots are thereby in direct contact with isolation material in the isolation slot to thereby inhibit end effects.

Walled slot devices and method of making same

The invention comprises an improved integrated circuit structure wherein an active device is formed in a silicon substrate for forming an intrinsic base region over a buried collector and an emitter is formed on the intrinsic base region to comprise three electrodes of the active device and at least one extrinsic base segment is formed in the substrate adjacent to the intrinsic base region to provide a contact for the intrinsic base; the improvement which comprises: separating the extrinsic base segment from the emitter formed on the intrinsic base to prevent the formation of a parasitic P-N junction between the extrinsic base and the emitter.

Method of making an integrated circuit structure with self-aligned

A method is presented for fabricating a bipolar semiconductor device utilizing a combination of junction isolation, oxide isolation, stepper lithography and plasma etching to produce an integrated circuit device having reduced device sizes and increased performance. The method includes the steps of removing portions of a masking layer to expose surface areas of an epitaxial layer, where first type isolation regions are then formed; then forming second type isolation regions in the epitaxial layer, and forming base, emitter and collector contact regions, also in the epitaxial layer; and forming conductive lines on the base, emitter and collector contact regions.

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Sunnyvale, CA, United States of America

Christopher O Schmidt