Globalfoundries Inc.

Globalfoundries U.S. Inc.

Christopher Nassar

Veeraraghavan S Basker

Daniel J Jaeger

Hui Zang

Brian Joseph Greene

Haigou Huang

Michael Vincent Aquilino

Jinsheng Gao

Keith Howard Tabakman

Kai Zhao

Qun Gao

Junsic Hong

Vishal Chhabra

Lin Hu

Ankur Arya

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Source/drain contact depth control

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

One illustrative method disclosed herein includes, among other things, forming a first fin having first and second opposing sidewalls and forming a first sidewall spacer positioned adjacent the first sidewall and a second sidewall spacer positioned adjacent the second sidewall, wherein the first sidewall spacer has a greater height than the second sidewall spacer. In this example, the method further includes forming epitaxial semiconductor material on the fin and above the first and second sidewall spacers.

Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices

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Ballston Spa, NY, United States of America

Christopher Nassar