Unisys Corporation

Other

Christopher N St John

William Lawrence Kozlowski

John D Vala

John Charles Gudenburr

Paul John McCarthy

Philip D Klug

Weston Morris

David A LaPorte

William Donald Chappell

A processor bus bridge includes a buffer space disposed between a first bus and a second bus. The first bus is operated in a first mode by a first processor and the second bus is operated in a second mode by a second processor. The first bus has an electrical structure which is different from the electrical structure of the second bus. The first mode may also differ from the second mode. The processor bus bridge has a protocol logic module disposed between the first processor and the second processor for controlling data transfer across the buffer space in the first and second modes. Thus, the bus bridge enables communications between dissimilar processor buses while increasing performance and reducing CPU overhead.

Multi-mode processor bus bridge

A method and system provide for real-time compensation of an imaging system for variations in illumination intensity. An illumination system provides reflected illumination, and a charge coupled device system directly detects the reflected illumination from the illumination system. The CCD system then converts the reflected illumination into illumination data and a host processor converts the illumination data into adjusted control data and final image data. The adjusted control data is based on an illumination profile and a reference illumination intensity. The reference illumination intensity is measured before each document with a compensation reference, and is compared to the illumination profile to adjust control parameters in a real-time mode. Directly measuring the illumination intensity with the CCD system allows for a reduction in parts, manufacturing steps, and errors.

Illumination compensation using built-in reference

A method and system for ink jet printing of characters in a variable rate document transport creates a correct column pitch for the document speed. An endorser control system includes a processor having a DMA unit for retrieving column data at a column data rate wherein the processor controls the variable document travel rate. The system further includes a sequencer for converting the column data into dot data. The DMA unit in conjunction with a compare match timer writes the column data from the processor memory to the sequencer at the specified column data rate.

Variable rate ink jet endorser

A method and configuration for interprocessor communication provides reduced latency and complexity, as well as the ability to simultaneously transfer different types of data. A multi-channel interface is disposed between a slave processor and a master processor, wherein the multi-channel interface has a low-latency channel for transferring low-latency information and a high-throughput channel for transferring high-throughput information. The master processor interrupts the slave processor when the master processor has control information to transfer to the slave processor. Interrupt driven notification and the multi-channel interface provide reliable, high-speed communication between dissimilar processors.

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Plymouth, MI, United States of America

Christopher N St John