Nxp Usa, Inc.

Freescale Semiconductor,inc.

Christopher N Hume

Jeffrey C Cunningham

Ross Sinclair Scouller

Jon Scott Choy

Timothy J Strauss

Maurits Mario Nicolaas Storms

Silvia Wagemans

A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

Column repair in a memory system using a repair cache

A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

System and method for low cost patching of high voltage operation memory space

Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

Digital control for regulation of program voltages for non-volatile memory (NVM) systems

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Kyle, TX, United States of America

Christopher N Hume