Aeroflex Colorado Springs Inc.

Promos Technologies, Inc

Christopher Mnich

Jonathan Mabra

Matthew S Von Thun

A method of incorporating active error correction inside a memory device is used, whereby memory scrub cycles can be completely hidden from an end user. The method simplifies the design of the memory interface and simplifies the data integrity management unit for the end user. An arbitration unit is implemented to allow concurrent processing of primary (user) and secondary (scrub) requests. The arbitration unit is location aware in context to the primary interface and is responsible for eliminating overlapping memory requests.

Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic

A phase-locked loop (PLL) circuit system includes first, second, and third PLL circuits, first, second, and third multiplexer circuits coupled to the first, second, and third PLL circuits, and a majority voter circuit coupled to the first, second, and third PLL circuits, wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit. Each PLL circuit includes a first input for receiving a reference clock signal; a second input for receiving a feedback clock signal; a first output for providing an output clock signal; a second output for providing a lock signal; and a return path coupled between the first output and the second input. The return path can be a direct connection or a logic circuit. Each multiplexer circuit includes three lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.

Method for creating a reliable phase-locked loop in a ruggedized or harsh environment

A clock generating circuit includes oscillators each having a delay rise vote input, a delay fall vote input, a delay rise output, a delay fall output, and a clock output; a vote rise circuit having inputs coupled individually to the delay rise outputs of the oscillators, and an output coupled in common to the delay rise vote inputs of the oscillators; a vote fall circuit having inputs coupled individually to the delay fall outputs of the oscillators, and an output coupled in common to the delay fall vote inputs of the oscillators; and a vote clock circuit having inputs coupled individually to the clock outputs of the oscillators, and an output for providing a synchronized clock signal.

Method for synchronizing a multiplicity of clock generating circuits

A column repair circuit uses a system of circuits that automatically stops the shifting of register contents independently of the number of bits to be shifted. The circuit is only dependent on the number of bits in a column address repair block. By adding shift register positions to one end of each shift register chain, a dedicated block of bits is used to detect the end of the shift chain without explicitly knowing the length of the chain. The shift register positions provide a hard-programmed code that can be used to stop the shifting of data automatically. The shift register positions also provide a space for hard-programmed code bits that can be examined to determine when the shift process ends. A shift chain can be controlled with a controller so long as the information is organized into groups of 'k' bits. The controller only requires information regarding the value of the number 'k' and the pre-programmed stop code in order to control any number of bits in a shift chain.

N-bit shift register controller

A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering.

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Colorado Springs, CO, United States of America

Christopher Mnich