Analog Devices,inc.

Christopher Michalski

David Graham Nairn

Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.

Switched-capacitor structures with enhanced isolation

Latch structures and systems are disclosed that enhance latch speed and provide complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to enhance regenerative feedback signals and generate CMOS-level latch signals.

BiCMOS latches with NPN control devices for current limiting of NPN regeneration devices

Improved differential amplifiers are provided for use with switched-capacitor structures. Amplifier embodiments include a differential pair of high-transconductance transistors for generation of differential currents and routing of common-mode feedback signals along an independent path so that sufficient headroom is provided for other high-transconductance transistors that generate common-mode currents. The differential and common-mode currents preferably generate differential and common-mode output signals in finite output impedances of active loads.

Amplifier common-mode feedback systems for use with switched-capacitor structures

High-speed differential amplifiers are provided for use with switched-capacitor structures. These amplifiers reduce current demand during small-signal operation and generate high slew currents during large-signal operation. These processes are realized with slew-current generation structures that directly generate slew currents during large-signal operation and thus avoid the degradation of intermediate current-genration structures.

Amplifier slew-rate enhancement systems for use with switched-capacitor structures

High-speed sampler methods and structures are provided to enhance the correlation between an input signal S and a corresponding sampler output voltage V . An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor C is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal S . In the holding time periods, the disabled input buffer is isolated from the sampling capacitor C and a common-mode signal S is directly coupled to the capacitor's bottom plate to provide the output voltage V at the capacitor's top plate. Preferably, an output capacitor C is coupled to the sampling capacitor C and charge from the sampling capacitor C is transferred to the output capacitor C .

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High Point, NC, United States of America

Christopher Michalski