Broadcom Corporation

Christopher Michael Ward

Jan Mulder

Ovidiu Bajdechi

Frank Van Der Goes

Klaas Bult

Franciscus Maria Leonardus Van Der Goes

Jan Roelof Westra

Marcel Lugthart

Pieter Vorenkamp

Rudy J Van De Plassche

Tom W Kwan

Frank Carr

Scott C Savage

Derek Tam

James Y C Chang

Bruce Howard Conway

Mark Berman

Ralph A Duncan

Manolito Catalasan

Haideh Khorramabadi

Stephen F Greenwood

Franciscus Van Der Goes

Erol Arslan

Ruby Van De Plassche

Josh Crohn

Iniyavan Elumalai

A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

High efficiency voltage level multiplier

A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.

Digital-to-analog converter using nonlinear capacitance compensation

A low-power level-shift circuit for data-dependent signals includes a buffer circuit, a coupling capacitor, and a biasing circuit. The buffer circuit is biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal. The coupling capacitor is coupled, at a first node, to an output node of the buffer circuit. The biasing circuit is coupled to a second node of the coupling capacitor and a switch. The level-shift circuit can translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.

Low-power level-shift circuit for data-dependent signals

A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.

Calibration of interleaving errors in a multi-lane analog-to-digital converter

In one method embodiment, receiving a data signal; and converting the data signal to an analog signal over plural clock cycles, the converting comprising: during a first clock cycle of the plural clock cycles, switching on one or more first current cells of a first bank while simultaneously a second bank comprising second current cells is switched off or almost off; and during a second clock cycle of the plural clock cycles, the second clock cycle immediately subsequent to the first clock cycle, switching on one or more of the second current cells of the second bank while simultaneously the first bank is switched off or almost off.

Interleaved return-to-zero, high performance digital-to-analog converter

An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.

Low-power ethernet transmitter

An output stage comprising a current mode line driver, a voltage mode line driver, and a center-tapped transformer for coupling data provided by the line drivers to a transmission line is provided herein. The output stage is configured to operate in a backwards compatible Ethernet communication device. For example, the Ethernet communication device is configured to support 10G Ethernet and legacy Ethernet modes of 10BASE-T, 100BASE-T, and 1000BASE-T. The current mode line driver can be utilized while operating in the 10G Ethernet mode to provide high linearity. The voltage mode line driver can be utilized while operating in legacy mode to conserve power. In order to accommodate the use of two different line drivers, a switch and/or a voltage regulator is used to couple/decouple a dc voltage to a center-tap of the transformer based on which of the two different line drivers is currently active.

Mode dependent driving of the center tap in ethernet communications

Aspects of a method and system for a power reduction scheme for Ethernet PHYs are provided. An Ethernet PHY in a link partner may disable transmission via a transmit DAC integrated during an inactive connection, 10Base-T autonegotiation operation, and/or active 10Base-T connection with no data packet transmission. The DAC may be a voltage mode or current mode DAC. The PHY or a MAC device may determine when to disable transmission via the DAC. In this regard, the PHY or the MAC device may generate appropriate signals for disabling the transmission. The DAC may be enabled for transmission by the PHY or the MAC device when a connection becomes active or when an active 10Base-T connection is ready to transmit data. Moreover, the PHY may enable transmission via the DAC when operating in a forced 10Base-T mode of operation and the connection to the link partner is active.

Method and system for a power reduction scheme for Ethernet PHYs

A compact low-power class AB power amplifier design is provided. In an embodiment, the amplifier design eliminates an intermediate stage that couples an input stage and a biasing mesh of the amplifier. In another embodiment, the amplifier design reuses a tail current from the input stage to bias the biasing mesh. Accordingly, a much higher power efficiency can be achieved using the proposed amplifier design compared to conventional class AB amplifiers. Further, the proposed amplifier design is extremely compact and occupies a small silicon area.

Compact low-power class AB amplifier

The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

ISI reduction technique

A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.

High-efficiency class-AB amplifier

A line driver for generating 10 BT signals is disclosed. Digital symbols to be transmitted via a 10 BT Ethernet line are converted by a digital-to-analog converter into a corresponding analog voltage signal, which is fed into an active output impedance line driver. The digital-to-analog converter also receives a reference voltage reflecting variations of the supply voltage and adjusts its output signal accordingly to provide a deliberately variable analog voltage signal to the line driver.

Techniques for enabling a 10BT active output impedance line driver using a low power supply

An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Subranging analog to digital converter with multi-phase clock timing

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Fully integrated tuner architecture

A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.

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Utrecht, Netherlands

Christopher Michael Ward