General Semiconductor of Taiwan, Ltd.

Christopher Michael Knowles

Yih-Yin Lin

Tung-Chieh Lin

William John Nelson

Hung-Ping Tsai

Richard Sean O'Rourke

A wafer-level process for fabricating a plurality of passivated semiconductor devices comprising the steps of providing a semiconductor wafer on that at least one p-n junction is formed, Cutting a plurality of grooves in said wafer to expose said at least one p-n junction, wherein each of said grooves extends partly through the wafer and has a depth that is enough to expose said at least one p-n junction, applying a passivating material into said grooves and curing the material. The grooves can be formed by using a disc saw having a blade, by performing a sandblasting operation within a controlled operation time, or by performing a photolithographically chemical etching process. The passivating material is either screen-printed or pin-dispensed into the grooves. A dicing operation can be subsequently proceeded to divide the wafer into individual chips for subsequent fabrication into completed semiconductor devices.

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Taipei, Taiwan

Christopher Michael Knowles