Texas Instruments Corporation

Christopher Michael Graves

Ball Fan

Wenpang David Wang

Baher S Haroun

Steven E Marum

James Craig Spurlin

Vikas Suma Vinay

David H Elwart, Ii

John Edward Esquivel

An audio accessory key detection system () includes a host circuit (-) coupled to communicate via a microphone line () with an accessory circuit (-) in either a MSFT mode or a digital communication mode. Depletion mode transistors (-) in the accessory circuit are coupled between keys (-) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

Operating a headset that includes microphone line and pushbutton keys

A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.

Gate control for a tristate output buffer

A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.

Level shifter for a wide low-voltage supply range

A circuit coupled to receive an input voltage that can span a wide voltage supply range and a voltage translator that includes the circuit are disclosed. The circuit includes a first metal oxide silicon (MOS) transistor having a first conductivity type and a first threshold voltage and a second MOS transistor having the first conductivity type and a second threshold voltage that is lower than the first threshold voltage. The first MOS transistor is coupled in parallel with the second MOS transistor between a first rail and a first signal line; the first MOS transistor and the second MOS transistor each receive a first signal on a respective gate.

Circuit having a parallel voltage threshold architecture to support a wide voltage supply range

Initial command to switch transistors disconnecting keys from microphone line

Self-grounded circuitry () includes a signal channel conducting an output voltage (V). A charge pump () powered by a reference voltage (V) produces a control voltage (V). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit () includes a depletion mode transistor (MP) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (-) and a parasitic substrate diode (D-). A negative voltage protection circuit (-) includes a depletion mode first protection transistor (MP-) having a drain coupled to the well region, a source coupled to a source of a depletion mode second protection transistor (MP-) having a drain coupled to the output voltage, the first and second protection transistors each having a gate coupled to the control voltage, and also includes a diode (MN) coupled to charge the well region from the control voltage conductor to prevent distortion of the output voltage.

Negative audio signal voltage protection circuit and method for audio ground circuits

Methods and apparatus for over-voltage protection of device inputs are disclosed. An example apparatus to protect a device from an over-voltage condition disclosed herein comprises a switch coupled between a device input and at least one component of the device, and a voltage compensator to pull a control input of the switch to a voltage associated with the device input to open the switch to protect the device component from the over-voltage condition.

Methods and apparatus for over-voltage protection of device inputs

An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during normal conditions. When the transistor is switched to the on state and the switch is closed, the gate voltage is applied to the backgate of the pass transistor in order to reduce the threshold voltage and the on resistance. During an undershoot condition, the gate of the pass transistor is connected to the negative voltage applied to an input port and this voltage is also connected to the backgate of the pass transistor to prevent the pass transistor from being biased on or the parasitic NPN transistor from being biased on and transmitting the input glitch to the output.

Signal switch with reduced on resistance and undershoot protection

An output driver includes a predriver circuit coupled to a complimentary MOS transistor pair. Third and fourth complimentary MOS transistors are coupled between a source-drain pair of the first and second MOS transistors, respectively and an output. The back gate of at least one of the third and fourth transistors is coupled to the output to provide a lower Vat the beginning of a transition without creating excessive undershoot or overshoot. A diode is coupled in parallel with the source-drain paths of the third and fourth transistors.

Bus driver

A CMOS bus switch ( ) having undershoot protection circuitry ( ) to help prevent data corruption when the switch is open and the buses (A,B) are isolated from one another. A bias generator ( ) sets a voltage (Bias) referenced to ground which allows the active pull-up clamp to turn on when the bus voltage goes negative. This clamp attempts to counteract the undershoot voltage and limit the Vgd or Vgs of the N-channel pass transistor (MN ) and the Vbe of the parasitic NPN transistor. Since the active pull-up clamp circuit is also over-voltage tolerant, this invention will work equally well in high, low, and mixed voltage systems.

Over-voltage tolerant, active pull-up clamp circuit for a CMOS crossbar switch

A low voltage CMOS bus switch (,) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (,) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref,, Dref,) when the supply (V,) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN,,MP,) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR,) turns off and a gate voltage of a N-channel pass transistor (MN,) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3.3V or 5V bus.

Low-power 5-volt input/output tolerant circuit with power-down control for a low voltage CMOS crossbar switch

A control circuit for a low-voltage bus switch where the control circuit keeps the bus switch open by stealing power from switch I/O terminals during the loss of supply voltage and thereby maintaining bus isolation. The control circuit also provides a good high level and presents a low switch impedance.

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Sherman, TX, United States of America

Christopher Michael Graves