Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Christopher Michael Brueggen

Keith D Underwood

Robert L Alverson

Jason Douglas Jung

Norell Estella Menhusen

Gregg Bernard Lesartre

Gary Belgrave Gostin

Derek Alan Sherlock

Harvey Ray

Michael Alex Schroeder

Elene Chobanyan

David M Olson

James Donald Regan

A network interface card (NIC) receives packets corresponding to a read or write request, the packets associated with a datatype descriptor stored in a datatype engine of the NIC, and each packet associated with a precomputed context which indicates a value for each dimension of a multi-dimensional array and a start location of the respective packet within a host memory block. The NIC generates, for a respective packet, a datatype handle corresponding to the datatype descriptor and an offset indicating a position of the respective packet within the packets. The NIC determines, based on the datatype handle and the offset, a cached context for the respective packet and initializes the datatype engine based on the cached context. The datatype engine generates, based on the cached context, read or write requests comprising addresses and lengths, thereby allowing the NIC to process out-of-order packets based on the precomputed and cached context.

Mechanism to enable out-of-order packet processing in a datatype engine

A system, method, and apparatus are provided to facilitate data structures for a datatype engine and provide inline compaction. The system receives, by a network interface card (NIC), a command to read data from a host memory, wherein the command indicates a datatype. The system generates a plurality of read requests comprising offsets from a base address and corresponding lengths based on the datatype. The system issues the plurality of read requests to the host memory to obtain the data from the host memory. The system obtains a byte-mask descriptor corresponding to the datatype. The system performs, based on the obtained data and the byte-mask descriptor, on-the-fly compaction of the obtained data, thereby allowing the NIC to return a requested subset of the obtained data.

Mechanism to represent data structures for a datatype engine and provide inline compaction

A virtual channel (VC) allocation system is provided. During operation, the system can maintain, at an ingress port of a switch, a set of counters. A respective counter can indicate a number of data units queued at a corresponding egress port for an ingress VC. A data unit can indicate a minimum number of bits needed to form a packet. The system can maintain, at an egress port, an ingress VC indicator indicating that a packet in an egress buffer for an egress VC corresponds to the ingress VC. Upon sending the packet, the system can update a counter based on the ingress VC indicator. The counter can be associated with the egress buffer and the ingress VC. The system can then issue, to a sender device, credits associated with the ingress VC based on a minimum number of available data units indicated by the set of counters.

Method and system for virtual channel remapping

Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.

Physical layer low-latency forward error correction

One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.

Method and system for enhanced queue management in a switch

In one example, a controller for managing a set of resources. A first structure has a first entry statically associated with one of the resources. A second structure has a second entry dynamically associative with one of the resources. A resource sharing mechanism borrows for the second structure an idle resource associated with the first structure.

Managing a set of resources

A method for detecting a persistent error in a digital memory is provided. Error location information for errors detected in the digital memory is received. A group of the errors that are associated with a same error position is identified from the error location information. A number of the errors of the group that are associated with a same area of the digital memory is identified. A persistent error is determined based upon the number of the errors of the group.

Persistent error detection in digital memory

Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.

Systems and methods for mitigating latency associated with error detection and correction

In one embodiment, a memory controller comprises a cache line processing block for processing a cache line into a plurality of segments, an error correction code (ECC) generation block that forms ECC code words for each of the plurality of segments for storage in a plurality of memory components, an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from the plurality of memory components, and an error seeding block that enables a respective error to be inserted into each ECC code word of the cache line in response to a plurality of error registers.

Systems and methods for providing error correction code testing functionality

In one embodiment, there is disclosed a system and method for mapping memory addresses to system memory by establishing the size and location of each memory rank within the system memory, establishing a total size of said system memory, and fitting each said memory rank into the system memory block by using a highest power of 2 fitting rule for each iteration such that each highest power of 2 for each iteration controls the allocation of memory ranks for each such iteration.

Growing community of inventors

Allen, TX, United States of America

Christopher Michael Brueggen