Lsi Logic Corporation

Lsi Corporation

Christopher McCarty

Stephen B Johnson

Timothy E Hoglund

Brad D Besmer

Guy Kendall

Jeffrey M Rogers

Andrew Carl Brown

Jeffrey J Gauvin

Bradley Dean Besmer

Wiliam Petty

Bruce Trunck

Margit C Evensta

A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Back-off retry with priority routing

A first SAS expander including at least phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.

Method and system for combining multiple SAS expanders into a SAS switch

A failed link is detected between a first SAS expander and a device. A data transfer of the first SAS expander connected to the device via the failed link is re-routed to a second SAS expander connected to the device via a functional link. The first SAS expander is connected to the SAS expander via the phys of the first SAS expander and the phys of the second SAS expander for inter-expander communications.

Method for providing path failover for multiple SAS expanders operating as a single SAS expander

The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.

Specifying lanes for SAS wide port connections

Methods and structure for enabling transparent coordination between multiple host systems sharing access to a common SATA storage device to improve bandwidth utilization therebetween in a manner transparent to each of the multiple host systems. The SAS protocol may be utilized by each of the host systems coupled to an SAS/SATA Converter. The storage device coupled to an output path of the SAS/SATA Converter is selectively coupled to one of the multiple host systems each coupled to an input signal path of the SAS/SATA Converter to the shared SATA storage device. Protocol conversion within the SAS/SATA Converter may convert between host SAS protocol exchanges and SATA protocol exchanges of the storage device. Other features within the SAS/SATA Converter may provide queuing or buffering of SAS protocol exchanges from a host system presently non-selected for coupling to the shared SATA storage device.

Methods and structure for a SAS/SATA converter

The present invention relates to a method, circuit, and system for performing write journal operations on a bus interface controller board or bus interface controller integrated circuit chip. This is achieved by placed a write journal memory on the board or chip and supplying power to it from an external power source. Preferably, the external power source is a battery. The internal memory may use bus interface controller power when available to prolong battery life.

Alternate non-volatile memory for robust I/O

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.

Request and completion queue load balancing

The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

Method and apparatus for embedding configuration data

Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.

Methods and apparatus for booting a host adapter device devoid of nonvolatile program memory

An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Method and/or apparatus to sort request commands for SCSI multi-command packets

A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.

Growing community of inventors

Colorado Springs, CO, United States of America

Christopher McCarty