Koninklijke Philips Corporation N.v.

Nxp B.v.

Christopher Martin Rogers

Steven Thomas Peake

Philip Rutter

Raymond J Grover

Georgios Petkos

Peter J Forbes

Robert J Farr

Miron Drobnis

Andrew Butler

A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.

Semiconductor device with gate trench

A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region () of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Trench gate MOSFET and method of manufacturing the same

A cellular MOSFET device has a cellular area (CA) comprising active MOSFET cells, and one or more Schottky diode areas (SA) accommodated within a deep end region () at a lateral boundary of this cellular area (CA). This deep end region () is laterally divided so as to accommodate the diode area (SA) therein. A diode portion () of the first conductivity type of the drain region () extends upwardly through the laterally-divided deep end region () that is of the second conductivity type. The Schotty barrier () formed with this diode portion () terminates laterally in the laterally-divided portions () which serve as a guard region and field-relief region for the Schottky diode.

Cellular mosfet devices and their manufacture

Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers ( ) in different ways. Thereby, the source region ( ) and a contact window ( ) for a source electrode ( ) can be self-aligned to a narrow trench ( ) containing the trench-gate ( ). Thereby, the channel-accommodating region ( ) can also be provided after forming the trench-gate ( ), and with very good control of its doping concentration (Na; p) adjacent to the trench ( ). To achieve this control, its dopant is provided after removing the spacers ( ) from the mask ( ) so as to form a doping window ( ), which may also be used for the source dopant, adjacent to the trench-gate ( ). A high energy dopant implant ( ) or other doping process provides this channel dopant adjacent to the trench ( ) and extending laterally below the mask ( ). A remarkably uniform doping profile can be achieved beneath the doping window ( ) and beneath the mask ( ). By using a high ion energy and high dose, the dopant ions ( ) at the doping window ( ) can be laterally scattered below the mask ( ) while those at the mask ( ) penetrate there-through to be implanted in the underlying portion of the body ( ).

Trench-gate semiconductor devices having a channel-accommodating region and their methods of manufacture

Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers ( ) in different ways. The trench-gate ( ) is accommodated in a narrow trench ( ) that is etched via a narrow window ( ) defined by the spacers ( ) at sidewalls of a wider window ( ) of a mask ( ) at the body surface ( ). The spacers ( ) permit a source region ( ) adjacent to the trench-gate ( ) and an insulating overlayer ( ) over the trench-gate ( ) to be self-aligned to this narrow trench ( ). The overlayer ( ), which defines a contact window ( ) for a source electrode ( ), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers ( ). Its overlap (y , y &prime;) with the body surface ( ) is well-defined, so reducing a short-circuit risk between the source electrode ( ) and the trench-gate ( ). Furthermore, implantation of the source region ( ) is facilitated, and a channel-accommodating region ( ) can also be provided using a high energy implant ( ) after providing the insulating overlayer ( ).

Growing community of inventors

Manchester, United Kingdom

Christopher Martin Rogers