Deca Technologies Inc.

Amkor Technology, Inc.

Other

Tyco Electronics Logistics Ag

Christopher Marc Scanlan

Timothy Lee Olson

Craig Bishop

Christopher J Berry

Ronald Patrick Huemoeller

William Boyd Rogers

Faheem F Faheem

Robert J Hill

John Armando Miranda

Frank Joseph Juskey

Ronald James Schoonejongen

Jon G Aday

Michael Paul Gaynor

Joseph Marco Longo

Pat O'Brien

Vaibhav Joga Singh Bora

Douglas Jay Mathews

Michael G Kelly

Roger D St Amand

Jae Dong Kim

Tim Olson

Kenneth Charles Blaisdell

Ferdinand Aldas

Sabbas A Daniel

Cheryl R Abanes

A method of making a semiconductor device can include providing a semiconductor die comprising a front surface comprising a gate pad and a source pad, the semiconductor die further comprising a back surface opposite the front surface, the back surface comprising a drain. A gate stud may be formed over and coupled to the gate pad. A source stud may be formed over and coupled to the source pad. An encapsulant may be formed over the semiconductor die. A through mold interconnect may extend between opposing first and second surfaces of the encapsulant. An RDL may be coupled to the gate stud, the source stud, and to the through mold interconnect. A land pad may be formed over the back surface of the semiconductor die and be coupled to the drain after singulating the semiconductor die from its native wafer and after forming the encapsulant over the semiconductor die.

Fully molded semiconductor package for power devices and method of making the same

A semiconductor device includes a molded core unit that includes a first semiconductor die with conductive interconnects and a second semiconductor with conductive interconnects. The first semiconductor die and the second semiconductor die are encapsulated by a single encapsulant that contacts at least four sides surfaces and an active surface of the first semiconductor die and the second semiconductor die, as well as side surfaces of the conductive interconnects. The molded core unit further includes a fine-pitch build-up interconnect structure disposed over the encapsulant and coupled to the conductive interconnects of the first semiconductor die and the conductive interconnects of the second semiconductor die interconnected without a silicon interposer. The molded core unit can be mounted to an organic multi-layer substrate. A heat sink may be coupled to the back surfaces of the first semiconductor die and the second semiconductor die with a thermal interface material (TIM).

Thermally enhanced fully molded fan-out module

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.

Method of making fully molded peripheral package on package device

A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.

Semiconductor device and method of unit specific progressive alignment

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

Fully molded miniaturized semiconductor module

A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

Method of marking a semiconductor package

A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.

Semiconductor device and method of packaging

A semiconductor device and method can comprise measuring a true position of each of a plurality of semiconductor die within an embedded die panel and determining a total radial shift of each of the plurality of semiconductor die. The total radial shift of each of the plurality of semiconductor die can be distributed to two or more layers for each of the plurality of semiconductor die by assigning a portion of the total radial shift to each of the layers according to a priority list to form a distributed radial shift for each of the layers. A transformation for each of the layers for each of the plurality of semiconductor die can be transformed using the distributed radial shift for each of the layers. A unit specific pattern can be formed over each of the plurality of semiconductor die with the transformation for each of the layers.

An automated optical inspection (AOI) system can comprise aligning a wafer comprising a plurality of unit specific patterns. A plurality of unique reference standards can be created as a plurality of electrical nets by generating with a computer an electrical net for each of the unit specific patterns, each of the plurality of electrical nets comprising a start point and an end point. An image of each of the plurality of unit specific patterns can be captured with a camera. The image can be processed with the computer to provide a plurality of extracted boundaries of contiguous electrically conductive regions. Defects in the plurality of unit specific patterns, if present, can be detected by comparing each of the extracted boundaries of contiguous electrically conductive regions to a corresponding one of the plurality of unique reference standards. An output of known good die can be created.

Automated optical inspection of unit specific patterning

A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating layer over the temporary carrier. Conductive pads can be formed within openings in the insulating layer and be positioned both within and without the die mounting area. A backside redistribution layer (RDL) can be formed over the temporary carrier before mounting a semiconductor die at the die mounting site. Conductive interconnects can be formed over the temporary carrier in a periphery of the semiconductor die mounting site. A semiconductor die can be mounted face up to the insulating layer. The conductive interconnects, backside RDL, and semiconductor die can be encapsulated with a mold compound. A build-up interconnect structure can be formed and connected to the semiconductor die and the conductive interconnects. The temporary carrier can be removed and the conductive pads exposed in a grinding process.

Fully molded peripheral package on package device

A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline.

Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping

An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.

Semiconductor device and method of adaptive patterning for panelized packaging

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

Semiconductor package in package

A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can be mounted face up to the temporary carrier such that back surfaces of the first semiconductor die and the second semiconductor die are depressed within the adhesive. An embedded die panel can be formed by encapsulating at least four sides surfaces and an active surface of the first semiconductor die, the second semiconductor die, and side surfaces of the conductive interconnects in a single step. The conductive interconnects of the first semiconductor die and the second semiconductor die can be interconnected without a silicon interposer by forming a fine-pitch build-up interconnect structure over the embedded die panel to form at least one molded core unit. The at least one molded core unit can be mounted to an organic multi-layer substrate.

Growing community of inventors

Chandler, AZ, United States of America

Christopher Marc Scanlan