International Business Machines Corporation

General Electric Company

Globalfoundries U.S. 2 LLC

Christopher M Schnabel

Terence B Hook

Francois Pagette

Melanie J Sherony

William R Tonti

Marwan H Khater

John Joseph Pekarik

Anna Wanda Topol

Rama Divakaruni

Gregory Gower Freeman

Hiroyuki Akatsu

Basanth Jagannathan

David C Ahlgren

Shreesh Narasimha

Richard Paul Volant

Anthony I Chou

James Stuart Dunn

Christopher Stephen Putnam

Anil Kumar Chinthakindi

Michael F Lofaro

Kenneth Jay Stein

Peter A Smith

BethAnn Rainey

Shwu-Jen Jeng

Nataniel Barbosa Vicente

Mark Fredrick Culler

John Edward Florkey

William Edward Ansley

Brian M Dufrene

Christopher H Lumbra

Mark Petersen

Karyn M Hurley

Embodiments of the present invention disclose a semiconductor structure and method for establishing a thermal profile across a semiconductor chip. In certain embodiments, the semiconductor structure comprises a through-silicon via formed in a first semiconductor chip having thermal control circuitry, wherein the through-silicon via is formed in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, and wherein the through-silicon via conducts heat from the thermal control circuitry to the region. In other embodiments, the method comprises forming a through-silicon via in a first semiconductor chip having thermal control circuitry. The method also comprises forming the through-silicon via in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, wherein the through-silicon via conducts heat from the thermal control circuitry to the region.

Establishing a thermal profile across a semiconductor chip

Methods for packaging a functional chip, methods for annealing a functional chip, and chip assemblies. A functional chip and an annealing chip are located inside a package. The functional chip includes an integrated circuit. The annealing chip includes an annealing element source comprised of an annealing element or a light source configured to emit electromagnetic radiation. The integrated circuit of the functional chip receives the annealing element, electromagnetic radiation, or both from the annealing chip in order to perform an annealing procedure that extends the useful lifetime of the packaged integrated circuit.

In-situ annealing for extending the lifetime of CMOS products

Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.

In-situ relaxation for improved CMOS product lifetime

Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Structure and layout of a FET prime cell

A method, computer program product, and system for enabling the merging of a plurality of instance variables into a new composite same-class instance having the same instance variables with values determined by a user. Same-class instances are arranged in tabular format and are provided with selection buttons to allow the user to make selections of the desired instance variable values.

Method, computer program product, and system for merging multiple same class instance states

A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.

Selectable device options for characterizing semiconductor devices

Carriers () holding parts () for assembling complex MEMS devices are transported to a central assembly location. The parts are stacked in a pre-assigned order and later released from their carriers. Alternatively, they are positioned over the appropriate location and released so as to fall into position as needed. The assembly area () includes a cavity below the plane of the carriers such that the parts held within the carrier drop into the cavity. Heating elements are integrated into the cavity to assist in the release of the parts. The cavity is supplied with parts by one or more carriers which are move around by any number of MEMS drive systems (). The cavity and some of the MEMS assembled therein deliver with precision amounts of materials as required suitable for biomedical applications, or may be processed in-situ, as in an on-chip laboratory.

Micro-electromechanical sub-assembly having an on-chip transfer mechanism

A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved f, Fmax and drive current.

Bipolar transistor with isolation and direct contacts

A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

Method of fabricating a bipolar transistor having reduced collector-base capacitance

Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.

Bipolar transistor having reduced collector-base capacitance

A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

Method of fabrication of MIMCAP and resistor at same level

An image of an integrated circuit chip and optical kerf and their mirror image are formed within a single optical field. When a substrate pattern using this process is flipped over or reversed, the processed pattern appears the same as on the first side, equal to its own mirror image. Prior to the backside lithography, a portion of the second side is removed to allow detection of alignment marks on the first side from the second side of the substrate. Once the alignment marks are detected, the lithography continues as though the substrate was not flipped over at all.

Method for backside alignment of photo-processes using standard front side alignment tools

A trip unit is provided with a microcontroller and non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memory, for storing trip setting values, including initializing parameters, boot code, and operational parameters being capable of analog or digital programming depending on a switching instruction. This configuration enables one to change the trip unit's trip setting values after it is manufactured either remotely or locally. The present invention provides thus increased functionality to trip units by enabling upgrades and servicing of the trip unit by downloading replacement trip setting values to it and having multiple operational parameters (trip setting values) available. This would include locally altering trip setting values and remotely downloading trip setting values when the electronic trip unit is connected to a host controller, such as a multi-purpose computer either directly, over the telephone lines, LAN or any other suitable connection such as the Internet.

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Poughkeepsie, NY, United States of America

Christopher M Schnabel