Intel Corporation

Christopher M Neumann

Jack T Kavalieros

Marko Radosavljevic

Seung Hoon Sung

Cheng-Ying Huang

Tahir Ghani

Stephen M Cea

Cory E Weber

Susmita Ghose

Varun Mishra

Gilbert W Dewey

Willy Rachmady

Patrick R Morrow

Hui Jae Yoo

Nicole K Thomas

Richard E Schenker

Ehren Mannebach

Anh Phan

Urusa Alaan

Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Forksheet transistors with dielectric or conductive spine

Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

Stacked forksheet transistors

Growing community of inventors

Portland, OR, United States of America

Christopher M Neumann