Agilent Technologies, Inc.

Christopher M Juenemann

John G Rohrbaugh

Peter Jacob Meier

Jeff Rearick

Brian C Miller

Michael R Diehl

Joel D Buck-Gengler

Dale Beucler

Kenneth S Bower

Rory L Fisher

Randy L Fiscus

Bradley J Goertzen

A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.

System and method for evaluating an integrated circuit design

An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

Integrated circuit with alternately selectable state evaluation provisions

Growing community of inventors

Aurora, CO, United States of America

Christopher M Juenemann