National Semiconductor Corporation

Other

Christopher M Hall

Gary D Phillips

David W Weinrich

Robert M Salter, Iii

William E Miller

Richard E Crippen

Frank James Cava

Jumana Muwafi

Kenneth E Dubowski

Rajat Sewal

A clip capable of magnetic attachment to a paintbrush or to a steel paint roller mesh tray. It has a hook arm extending from the body of the clip that enables a hanging attachment to a plethora of different sized paint cans and at different vertical angles. The clip may be used with continued attachment to the paintbrush where the paintbrush is hung on the paint can when necessary by the hook arm. It may also be used with continued attachment to a steel paint roller mesh tray and the paintbrush is magnetically affixed on the tray when necessary. A ferromagnetic backing cup may be used to direct the bulk of the magnetic flux to either side of the clip body.

Paintbrush clip

A canine protective suit comprising a face mask, a upper body protector and a lower body protector, wherein the face mask is removably secured to the upper body protector, and wherein the lower body protector is removably secured to the upper body protector. The upper body protector comprises elastic bands, wherein the elastic bands secure at least two front leg panels. Similarly, the lower body protector comprises elastic bands, wherein the elastic bands secure at least two back leg panels. To use, a canine's two front legs are placed into the two front leg panels as the upper body protector is placed on the canine. Similarly, the canine's rear legs are inserted into the back leg panels as the lower body protector is installed on the canine. The face mask is then disposed on the canine's face and secured to the upper body protector.

Canine protective suit and method of use thereof

A solar tracker operates on a single axis, but partially simulates a dual-axis tracker by adjusting tilt angle as the tracker rotates. The tracker is disclosed in particular embodiments which fit efficiently within a hemispherical transparent dome.

Solar tracker

A modular reusable bus architecture enhances testability of an integrated computer system in which multiple modules communicate over a system bus. Under the modular reusable bus architecture, the system bus can be configured to operate in different operation modes. In one embodiment, the bus architecture provides a test mode for testing an individual module within the integrated computer system, separate from the other modules. In another embodiment, the bus architecture configures the system bus to provide access to configuration registers and memory units disposed within each module, otherwise inaccessible in normal system operation. The modular reusable architecture can support any types and any number of modules, including modules incorporating analog and digital circuitry, and modules operating under different clock domains.

Modular re-useable bus architecture

A microprocessor which has a secure read only memory is disclosed. The secure read only memory provides for storage of a program and security to protect that program.

Microprocessor with secure programmable read only memory circuit

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.

Non-volatile memory control and data loading architecture for multiple

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.

Serial register multi-input multiplexing architecture for multiple chip

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package. In other modes of operation, however, the signals input from (or output to) the feed-through package pads are re-routed by transfer gates to the non-volatile memory die.

Multiple chip package processor having feed through paths on one die

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.

Multiple chip processor architecture with reset intercept circuit

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

Multiple chip processor architecture with memory interface control

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.

In-system programming architecture for a multiple chip processor

An EPROM register is programmed in a manner substantially similar to the manner used to program a main EPROM array contained on the same integrated circuit. Data in the main EPROM array must be read out by applying appropriate address and output enable signals. The EPROM register allows the data stored therein to be available at all times by providing a full-time static output signal. The register includes a static evaluation circuit for determining the data stored in the register, a precharge keeper circuit for providing a pseudo-static evaluation of the data, as well as providing a periodic refresh of the sense node during pseudo-static evaluation, and a margin test circuit for testing the threshold voltage of the register, as well as actual or relative shifts in the threshold voltage. The EPROM register serves as a nonvolatile memory which can be written to store configuration information for an integrated circuit.

EPROM register providing a full time static output signal

An integrated circuit which will produce a switched output when the circuit power supply drops a predetermined level below which reliable IC operation is not assured. This reduced power supply condition is referred to as brownout wherein the switching is related to the active devices. A preferred CMOS circuit is disclosed. The switching level is related to the N channel and P channel transistor sum of thresholds which makes the CMOS circuit process adaptive. The circuit is provided with a transistor gate oxide capacitor for improving noise immunity while achieving maximum utilization of IC chip area. In addition, output enable and circuit shutdown capabilities are detailed.

Noise resistant low voltage brownout detector with shut off option

A fault tolerant circuit and method of synchronizing multiple asynchronous input signals, such as reset signals, in a modular redundant fault-tolerant computer system in which clock signals or respective slices have a bounded skew with respect to one another. The input signal and clock signal for each slice of the system are used to produce an initial synchronization signal in each slice of a first layer of the circuit. Each initial synchronization signal is used with an inverted version of each of the slice clock signals to produce, in each slice of a second layer of the circuit, a set of local synchronization signals for each slice. The local synchronization signals for each slice are passed to a majority-voter which produces a voted output signal for the slice. The voted output signal and the clock signal for each slice are then used to produce a finally synchronized output signal for that slice. The output signals for the multiple slices are synchronized to the respectively associated slice clock signals, and to one another within the bounded skew of the slice clock signals.

Methods and circuits for synchronizing signals in a modular redundant

A Gray Code counter is provided having synchronous, modular circuits for each of the three types of bit positions, i.e., least significant bit ('LSB'), most significant bit ('MSB') and middle bit ('MB'). One LSB and MSB circuit each are used with as many MB circuits in between as are necessary to provide a counter having the desired number of bits. The LSB, MSB and MB circuits' designs are truly modular in that duplicate MB circuits can be freely coupled together between an LSB circuit and an MSB circuit to provide the desired number of counter bits without modifying any input or output interfaces between the circuits. The counter can count either up or down in accordance with a normal Gray Code sequence.

Growing community of inventors

Redwood City, CA, United States of America

Christopher M Hall